Acromag AcroPack AP560, User Manual

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AcroPack Series AP560 CAN Bus Interface Module
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Table 4 AP560 Memory Map
Description Base Addr+
Board Interrupt Register 00
Location Register 04
Channel Interrupt Pending
Register
08
XADC Status/Control 60
XADC Address 64
Channel 0 Registers 100
Channel 1 Registers 140
Channel 2 Registers 180
Channel 3 Registers 1C0
Firmware Revision Register 200
Board Interrupt Register, (Read/Write) - (Base + 00H)
This read/write register is used to enable board interrupt, determine the
pending status of interrupts.
The function of each of the interrupt register bits are described in Table 5. A
power-up or system reset sets all interrupt register bits to 0.
With both, the Board Interrupt Enable bit and a CAN Controller Interrupt
Enable bit, interrupts can be generated.
Table 5 Board Interrupt Register
BIT FUNCTION
0 Board Interrupt Enable Bit - This bit must be set to logic
“1” to enable generation of interrupts from the AP module.
Setting this bit to logic “0” will disable board interrupts.
(Read/Write Bit)
1 Interrupt Pending Status Bit - This bit can be read to
determine the interrupt pending status of the AP module.
When this bit is logic “1” an interrupt is pending and will
cause an interrupt request if bit-0 of the register is set.
When this bit is logic “0” an interrupt is n ot being
requested.
31:2 Not Used
Notes (Table 5):
1. All bits labeled “Not Used” will return logic “0” when read .