Acromag AcroPack AP560 User Manual Download

Page: 58 / 73

AcroPack Series AP560

CAN Bus Interface Module

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Table 30 Standard Frame Message

Offset
Address

Byte Content

Bit Description

0x10

Message Tag

MT7

MT6

MT5

MT4

MT3

MT2

0x11

ID28 to ID21

ID28

ID27

ID26

ID25

ID24

ID23

ID22

ID21

0x12

ID20 to ID18, RTR,
IDE

ID20

ID19

ID18

RTR

IDE

0x13

r0, DLC3 to DLC0

DLC3

DLC2

DLC1

DLC0

0x14

Data Byte 1

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0x15

Data Byte 2

0x16

Data Byte 3

0x17

Data Byte 4

0x18

Data Byte 5

0x19

Data Byte 6

0x1A

Data Byte 7

0x1B

Data Byte 8

Table 31 Extended Frame Message

Offset
Address

Byte Content

Bit Description

0x10

Message Tag

MT7

MT6

MT5

MT4

MT3

MT2

0x11

ID28 to ID21

ID28

ID27

ID26

ID25

ID24

ID23

ID22

ID21

0x12

ID20 to ID18, SRR,
IDE, ID17 to ID15

ID20

ID19

ID18

SRR

IDE

ID17

ID16

ID15

0x13

ID14 to ID7

ID14

ID13

ID12

ID11

ID10

ID9

ID8

ID7

0x14

ID6 to ID0, RTR

ID6

ID5

ID4

ID3

ID2

ID1

ID0

RTR

0x15

r0, r1, DLC3 to DLC0

DLC3

DLC2

DLC1

DLC0

0x16

Data Byte 1

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0x17

Data Byte 2

0x18

Data Byte 3

0x19

Data Byte 4

0x1A

Data Byte 5

0x1B

Data Byte 6

0x1C

Data Byte 7

0x1D

Data Byte 8

Table 32 Transmit History FIFO Format

Offset
Address

Byte Content

Bit Description

0x20

Message Tag

MT7

MT6

MT5

MT4

MT3

MT2

0x21

Time Tag Upper Byte

TT15

TT14

TT13

TT12

TT11

TT10

TT9

TT8

0x22

Time Tag Lower Byte

TT7

TT6

TT5

TT4

TT3

TT2

TT1

TT0

Summary of Contents for AcroPack AP560

Page 1: ...R S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road Wixom MI 48393 7037 U S A Tel 248 295 0310 Email solutions acromag com Copyright 2018 Acromag Inc Printed in the USA Data and specifications are...

Page 2: ...9 Logic Interface Connector 14 2 PROGRAMMING INFORMATION 15 PCIe Configuration Address Space 16 Configuration Registers 16 MEMORY MAP 17 Board Interrupt Register Read Write Base 00H 18 Location Regist...

Page 3: ...ment Sync Seg 38 Propagation Time Segment Prog Seg 38 Phase Buffer Segment 1 and Phase Buffer Segment 2 Phase Seg1 and Phase Seg2 39 Sample Point 39 Phase Errors e 40 Synchronization 40 Examples 40 RE...

Page 4: ...eral Sequence of Events for Processing an Interrupt 63 3 THEORY OF OPERATION 64 CAN BUS PHYSICAL CONNECTION 64 CARRIER INTERFACE 64 PCIe INTERFACE LOGIC 64 AP560 CONTROL LOGIC 64 CAN Transceiver 65 4...

Page 5: ...opyright Information 2018 by Acromag Incorporated All rights reserved Acromag and Xembedded are registered trademarks of Acromag Incorporated All other trademarks registered trademarks trade names and...

Page 6: ...res below 65 C the module will require a minimum airflow of 200LFM Mini PCIe x1 PCIe FPGA Field I O FLASH CAN transceiver CAN controller CAN transceiver CAN controller CAN transceiver CAN controller C...

Page 7: ...e directly to all Acromag AcroPack carriers Once installed on the carrier the module is accessed via a front panel connector The following cable is available for AcroPack carriers with the 68 pin CHAM...

Page 8: ...ring system This is especially important where personal injury or the loss of economic property or human life is possible It is important that the user employ satisfactory overall system design It is...

Page 9: ...he dense packing of the AcroPack module to the carrier CPU board restricts air flow within the card cage and is cause for concern Adequate air circulation must be provided to prevent a temperature ris...

Page 10: ...p Carrier3 Connector 50 Pin Champ Carrier2 Connector2 Ribbon Carrier Connector1 Module P2 Pin Number Field I O Signal 1 1 1 2 CAN0H 35 26 2 1 CAN0L 4 Reserved isolation 3 Reserved isolation 2 2 3 6 Re...

Page 11: ...Reserved isolation 9 9 17 34 CAN1H 43 34 18 33 CAN1L 36 Reserved isolation 35 Reserved isolation 10 10 19 38 Reserved isolation 44 35 20 37 RTN1 40 Reserved isolation 39 Reserved isolation 11 11 21 42...

Page 12: ...41 32 61 Reserved isolation 64 Reserved isolation 63 Reserved isolation 17 17 33 66 CAN2H 51 42 34 65 CAN2L 68 Reserved isolation 67 Reserved isolation 18 18 35 70 Reserved isolation 52 43 36 69 RTN2...

Page 13: ...ation 88 Reserved isolation 87 Reserved isolation 23 23 45 90 Reserved isolation 57 48 46 89 Reserved isolation 92 Reserved isolation 91 Reserved isolation 24 24 47 94 CAN3H 58 49 48 93 CAN3L 96 Reser...

Page 14: ...the mating connector on the carrier board The pin assignments of this connector are standard for all AP modules according to the PCI Express MINI Card Electromechanical Specification REV 1 2 with exce...

Page 15: ...C UIM_DATA 1 7 CLKREQ 1 8 N C UIM_PWR 1 5 TCK COEX2 1 6 N C 1 5V 1 3 TMS COEX1 1 4 GND 1 N C WAKE 1 2 3 3V3 Note 1 Signals are not applicable for the AP560 implementation Pins are either no connects o...

Page 16: ...registers to determine how many blocks of memory space the module requires It then programs the board s configuration registers with the unique memory address range assigned The configuration registe...

Page 17: ...or ID 16D5 12 Not Used 13 14 Reserved 15 Max_Lat Min_Gnt Inter Pin Inter Line MEMORY MAP This board is allocated a 2K byte block of memory that is addressable in the PCIe bus memory space to control t...

Page 18: ...er up or system reset sets all interrupt register bits to 0 With both the Board Interrupt Enable bit and a CAN Controller Interrupt Enable bit interrupts can be generated Table 5 Board Interrupt Regis...

Page 19: ...ese bits identify the slot location of the AP module in a system The Carrier may use backplane signals as in a VPX system or a carrier DIP switch to uniquely identify the system location of the carrie...

Page 20: ...e the interrupt pending status of the Channel 3 CAN controller When this bit is logic 1 an interrupt is pending and will cause an interrupt request if bit 0 of the Board Interrupt Register is set When...

Page 21: ...bed in Table 11 Table 11 Control Register BIT FUNCTION 0 Frequency Select selects the frequency of the oscillator input to the CAN controller This is the fOSC used in the bit rate calculation 0 32 MHz...

Page 22: ...Input Message Registers Table 14 Input Message Registers Bits Addr 31 24 23 16 15 8 7 0 20 Byte 3 Byte 2 Byte 1 Byte 0 24 Byte 7 Byte 6 Byte 5 Byte 4 28 Byte 11 Byte 10 Byte 9 Byte 8 2C Byte 15 Byte...

Page 23: ...ess register with a valid address for the XADC internal status or control registers Valid addresses are given in the following table Additional addresses can be found in the Xilinx XADC document UG480...

Page 24: ...nitialization Mode Initialization mode is used to configure the device before normal operation Initialization mode is the default mode following RESET and can also be activated by programming the MODE...

Page 25: ...transmit FIFO is empty In this mode the internal oscillator and all analog circuitry transceiver are off drawing typically less than 20 A Note that the SPI bus is active during sleep mode so it is po...

Page 26: ...re 2 The frame starts with a Start of Frame SOF bit This is a dominant bit that identifies the start of the data frame on the bus The SOF is followed by the 12 bit arbitration field The arbitration fi...

Page 27: ...writing the recessive bit of the transmitter The final bit in the ACK field is a recessive ACK delimiter bit Therefore the dominant ACK slot bit is surrounded on each side by a recessive bit Each dat...

Page 28: ...AcroPack Series AP560 CAN Bus Interface Module 28 Figure 2 Standard Data Frame...

Page 29: ...arbitration see Bitwise Arbitration section below The SRR and IDE bits are followed by the remaining 18 bits of the identifier extended ID and the last bit of the arbitration field is the RTR bit The...

Page 30: ...AcroPack Series AP560 CAN Bus Interface Module 30 Figure 3 Extended Data Frame...

Page 31: ...Simultaneous transmission of remote frames with the same identifier and different DLCs will lead to unresolvable collisions on the bus For this reason ARINC 825 strongly discourages the use of remote...

Page 32: ...AcroPack Series AP560 CAN Bus Interface Module 32 Figure 4 Remote Frame...

Page 33: ...lowed by the error delimiter consisting of 8 recessive bits Passive Error Flag A passive error flag consists of 6 recessive bits This is followed by the 8 recessive bits of the error delimiter Therefo...

Page 34: ...AcroPack Series AP560 CAN Bus Interface Module 34 Figure 5 Error Frame...

Page 35: ...ing the interframe space There are two types of overload frames 1 Reactive Overload Frame resulting from a detection of a dominant bit during the first or second bit of intermission b detection of a d...

Page 36: ...data contention on the bus using a scheme called Carrier Sense Multiple Access Collision Detection Carrier Resolution CSMA CDCR Carrier Sense Each node waits for a period without bus activity bus idle...

Page 37: ...l bit times as a function of bit time quanta see section on bit timing Synchronization takes place on recessive to dominant edges A Hard Synchronization at the start of each frame and subsequent re sy...

Page 38: ...bit rate is related to the TQ clock period by the following relationship BR 1 tTQ x number of time quanta per bit 3 The CAN standard divides the bit time into four segments namely synchronization seg...

Page 39: ...sample point is the point in the bit time at which the bit logic level is interpreted It is located at the end of Phase Seg1 The HI 3111 also allows three sample points to be taken In this case two o...

Page 40: ...to the edge causing the re synchronization For e 0 Phase Seg 1 is lengthened by the magnitude of the phase error up to a maximum of SJW For e 0 Phase Seg 2 is shortened by the magnitude of the phase...

Page 41: ...CODE CTRL0 R W Control Register 0 0x14 0xD2 CTRL1 R W Control Register 1 0x16 0xD4 BTR0 R W Bit Timing Register 0 0x18 0xD6 BTR1 R W Bit Timing Register 1 0x1A 0xD8 TEC R W Transmit Error Counter Regi...

Page 42: ...et to zero and resume operation in Normal Mode 0 The host is responsible for buss off recovery default 1 Automatic buss off recovery 3 RESET Setting this bit causes the HI3111 reset to occur Following...

Page 43: ...this mode Receive filters can be programmed in Initialization Mode to buffer selected messages 011 Sleep Mode The HI 3111 can be placed in a low power sleep mode if there is no bus activity and the tr...

Page 44: ...e Time Triggered CAN standard TTCAN Note un transmitted messages will remain in the FIFO If a new message is required on the next transmission cycle the user must first clear the FIFO with command 0x5...

Page 45: ...es the system oscillator frequency fOSC to the CAN bit time as described in the bit timing section 000000 BRP 1 000001 BRP 2 111111 BRP 64 7 6 SJW 1 0 Re synchronization Jump Width bits 1 0 These bits...

Page 46: ...0 Tseg1 3 Tq clock cycles 0011 Tseg1 4 Tq clock cycles 1111 Tseg1 16 Tq clock cycles Notes ARINC825 states that the sample point shall not be less than 75 of the bit time In this case Tseg1 should be...

Page 47: ...te a hardware interrupt if BUSOFFIE bit is set in STATFE register The HI 3111 will after entering bus off state automatically recover to error active status without host intervention if the BOR bit is...

Page 48: ...ived messages 0000 No filter matches the received message 1000 Filter 0 matches but filters 1 2 3 4 5 6 or 7 may also match 1001 Filter 1 matches filter 0 does not but filters 2 3 4 5 6 or 7 may also...

Page 49: ...rror CRC Error A CRC error was detected in a receive frame 3 FRMERR Form Error A Form error was detected in a receive frame 4 BITERR Bit Error A bit error was detected in a transmitted frame the bit o...

Page 50: ...er one passes a valid message FILHIT3 0 bits will also be set to 1001 in the Message Status Register MESSTAT 2 WAKEUP Wake Up detected This bit is set when the HI 3111 wakes up from Sleep Mode in resp...

Page 51: ...nerated at the INT pin when the WAKEUP bit is set in the INTF register 3 MCHGIE Enable interrupt when a mode change occurs Setting this bit causes a hardware interrupt to be generated at the INT pin w...

Page 52: ...IFO is full 1 RXFMTY Receive FIFO empty This bit is set when the receive FIFO is empty This is the default following reset 2 BUSOFF Busoff indicator This bit is set when the device enters bus off stat...

Page 53: ...yte bits 7 0 Command Summary Table 29 lists the available HI 3111 commands that are applicable to the AP560 Table 29 Command Summary Read Commands Code Data bytes Description Read Temporary Receive Bu...

Page 54: ...0xFA 2 see Free Running Timer Reset Commands Code Data bytes Description Abort Transmission stops current transmission and resets TXEN TX1M 0x52 None see Control Register 1 Reset Clear Transmit FIFO...

Page 55: ...f TXEN is not enabled messages will not be sent until TXEN is set If TXEN is reset a single message may also be sent by setting the TX1M bit in CTRL1 MESSAGE TRANSMISSION SEQUENCE A simplified transmi...

Page 56: ...to the Channel X output message registers for the selected channel Next the host must write command code 0x12 to the Channel X command register For standard frames the data field has the format shown...

Page 57: ...use TX1M bit 6 Register CTRL1 When using TX1M for single frame transmission TXEN should be low Following a successful transmission TXEN should be reset and the FIFO re loaded with the next message A...

Page 58: ...ion 7 6 5 4 3 2 1 0 0x10 Message Tag MT7 MT6 MT5 MT4 MT3 MT2 x x 0x11 ID28 to ID21 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 0x12 ID20 to ID18 SRR IDE ID17 to ID15 ID20 ID19 ID18 SRR IDE ID17 ID16 ID15...

Page 59: ...Filtering is enabled by setting the FILTON bit in Control Register 1 CTRL1 It the FILTON bit is not set then filtering is globally disabled and all CAN IDs are accepted There is a specific instruction...

Page 60: ...As can be seen in Table 35 bits specific to extended frames will be read as zeros for standard frames If the received data does not contain an 8 byte payload 8 data bytes the HI 3111 will pad the rem...

Page 61: ...FID4 FID3 FID2 FID1 FID0 x 0x14 Data Byte 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0x15 Data Byte 2 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Table 34 Mask ID Format Offset Address Byte Content Bit Description 7 6 5...

Page 62: ...TT4 TT3 TT2 TT1 TT0 0x23 ID28 to ID21 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 0x24 ID20 to ID18 SRR IDE ID17 to ID15 Note SRR and ID17 to ID15 are read as zeroes for standard frames ID20 ID19 ID18 SRR...

Page 63: ...Determine the IRQ line assigned to the AP560 during system configuration read configuration register number 15 3 Set up the system interrupt vector for the appropriate interrupt 4 Unmask the IRQ in t...

Page 64: ...e PCIe interface is imbedded within the FPGA This interface includes support for PCI commands including configuration read write and memory read write In addition the PCIe endpoint uses a single 2K ba...

Page 65: ...e 65 CAN Transceiver The ADM3053 CAN transceivers create a fully isolated interface between the CAN controllers and the physical layer bus These devices have current limiting and thermal shutdown feat...

Page 66: ...rectly is a good technique to isolate a faulty module CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS WHERE TO GET HELP If you continue to have problems your next step should be t...

Page 67: ...EC 61000 4 2 Radiated Field Immunity RFI per IEC 61000 4 3 Electrical Fast Transient Immunity EFT per IEC 61000 4 4 Surge Immunity per IEC 61000 4 5 Conducted RF Immunity CRFI per IEC 61000 4 6 Emissi...

Page 68: ...n 1 2 5GT s with 10 bit encoding there is a 20 loss in possible throughput due to encoding giving 2 0 G bits sec or 250M Bytes sec Note 2 A header for address and read write command is sent with every...

Page 69: ...60 CAN Bus Interface Module 69 6 APPENDIX AP CC 01 Heatsink Kit Installation This example will show how to install the AP CC 01 Heatsink kit with an APCe7020 carrier AP CC 01 Heat Sink Kit Bottom view...

Page 70: ...AcroPack Series AP560 CAN Bus Interface Module 70 1 Install two standoffs and secure with two screws 2 Install the AcroPack module 3 Install the Heatsink and secure with 4 screws...

Page 71: ...AcroPack Series AP560 CAN Bus Interface Module 71 4 AP CC 01 Installation is complete Note Make sure the thermal pad is contacting the FPGA IC...

Page 72: ...o Function Data storage for FPGA Process to Sanitize Power Down Non Volatile Memory Does this product contain Non Volatile memory i e Memory of whose contents is retained when power is removed Yes No...

Page 73: ...in the table below Release Date Version EGR DOC Description of Revision 28 MAR 2018 A ENZ MJO Initial Release 08 AUG 2018 B ENZ MJO Added power requirements 29 MAY 2019 C ENZ ARP Edited physical speci...

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