3-22 Chapter3
BF6
Video RAM Cacheable:
You can select Enable or Disable. When you select Enabled, you get faster video RAM
executing speed via the L2 cache. You must check your VGA adapter manual to find out if
any compatibility problems will occur.
8 Bit I/O Recovery Time:
Nine options are available: NA
,
8
,
1
,
2
,
3
,
4
,
5
,
6
,
7
,
Back to NA.
This
option specifies the length of a delay inserted between consecutive 8 bit I/O operations. For
an earlier 8 bit Add-on card, sometimes you need to adjust its recovery time to make it work
normally.
16 Bit I/O Recovery Time:
Five options are available: NA
,
4
,
1
,
2
,
3
,
Back to NA. This option specifies
the length of a delay inserted between consecutive 16 bit I/O operations. For an earlier 16 bit
Add-on card, sometimes you need to adjust its recovery time to make it work normally.
Memory Hole At 15M-16M:
Two options are available: Enabled
and Disabled. The default setting is
Disabled
. This
option is used to reserve the memory block 15M-16M for ISA adapter ROM. Some special
peripherals need to use a memory block located between 15M and 16M, and this memory
block has a size of 1M. We recommend that you disable this option.
Passive Release:
Two options are available: Enabled and Disabled. Set the option to enabled or disabled
passive release for the Intel PIIX4 chip (Intel PCI to ISA bridge). This function is used to
meet the latency of the ISA bus master, if you have an ISA card compatibility problem, you
can try to enable or disable this option for optimal result.
Delayed Transaction:
Two options are available: Enabled and Disabled. The default setting is
Disabled
. Set the
option to enabled or disabled PCI 2.1 features including passive release and delayed
transaction for the chipset. This function is used to meet the latency of PCI cycles to or from
the ISA bus. This option must be enabled to provide PCI 2.1 compliance. If you have an ISA
card compatibility problem, you can try to enable or disable this option for optimal results.
Summary of Contents for AB-BF6
Page 2: ......
Page 10: ...1 6 Chapter1 BF6 1 4 The System Block Diagram Figure 1 3 System diagram of the 440BX chipset ...
Page 84: ...B 6 Appendix B BF6 ...
Page 88: ...C 4 Appendix C BF6 ...
Page 90: ...D 2 Appendix D BF6 ...
Page 106: ...G 6 Appendix G BF6 ...