Zte ZXR10 8900E series, Описание продукта

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ZXR10 8900E series Core Switch Product Description
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4.2.1 Overall Hardware Architecture
ZXR10 8900E series switch adopts rack design to implement a system architecture with
separated forwarding plane, control plane and monitoring plane. The three planes work
and implement system functions together. The system uses new-generation
large-capacity high-speed serial bus back plane to connect main control switching card
and all service line cards. The main control card and switching matrix are integrated in
one, which supports 1:1 redundancy design. The main control switching card implements
porotcol and signaling processing, fast data switching, system monitoring, clock
synchronization, and maintenance & management. The main control card adopts
super-large-capacity switching matrix to guarantee the switching capacity necessary for
system wire-speed operation. Main control card uses high-performance CPU and
large-capacity memory to guarantee high-speed protocol processing and storage space
for huge table capacity. Each line card provides wire-speed packet processing capability
by ASIC and provides 10G, GE, 100M and 40G interfaces based on service requirements.
Each line card clock modules implement time and frequency synchronization by
exchange between clock bus and main control clock module, so as to provide reliable
and quality guarantee for clock synchronization. The main control node on the main
control card manages the monitoring node on line cards and collect the monitoring
information on the line cards by the monitoring bus, in order to realize intelligent
management of the equipment. Figure 4-9 and Figure 4-10 are hardware system
architecture diagram of ZXR10 8900E.
Figure 4-9 ZXR10 8912E/8908E/8905E hardware system architecture
Figure 4-10 ZXR10 8902E hardware system architecture