Z8018x
Family MPU User Manual
UM005004-0918
99
Table 14 describes all DMA TRANSFER mode combinations of DM0
DM1, SM0 SM1. Because I/O to/from I/O transfers are not implemented,
12 combinations are available.
Table 13. Channel 0 Source
SM1
SM0
Memory/I/O
Address lncrement/Decrement
0
0
Memory
+ 1
0
1
Memory
-1
1
0
Memory
fixed
1
1
I/O
fixed
Table 14. Transfer Mode Combinations
DM1 DM0 SM1 SM0 Transfer Mode
Increment/Decrement
0
0
0
0
Memory
to
Memory
SAR0+1, DAR0+1
0
0
0
1
Memory
to
Memory
SAR0-1, DAR0+1
0
0
1
0
Memory*
to
Memory
SAR0 fixed, DAR0+ 1
0
0
1
1
I/O
to
Memory
SAR0 fixed DAR0+1
0
1
0
0
Memory
to
Memory
SAR0+1, DAR0-1
0
1
0
1
Memory
to
Memory
SAR0-1,DAR0-1
0
1
1
0
Memory
to
Memory
SAR0 fixed, DAR0-1
0
1
1
1
I/O
to
Memory
SAR0 fixed. DAR0-1
1
0
0
0
Memory
to
Memory*
SAR0+ 1, DAR0 fixed
1
0
0
1
Memory
to
Memory*
SAR0-1, DAR0 fixed
1
0
1
0
Reserved
1
0
1
1
Reserved
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