Theory of Operation
Table 3-1
Chip Size Combinations.
Row A
Row B
Switch 1
654321
16K
†
16K
†
000000
32K
†
32K
†
001001
64K
†
32K
†
001010
64K
†
64K
†
010010
128K †
32K
†
001011
128K †
128K †
011011
256K †
128K †
011100
256K †
256K †
100100
512K †
—
xxx101
1M
**
—
xxx110
512K *
256K †
100111
512K *
512K *
101111
*
2 chips (sockets 4 and 5) max; e.g., use Row A for RAM and Row B for PROM.
**
2 chips (sockets 4 and 5) only, due to 2 Mbyte board limit.
†
1, 2, 3, or 4 chips per row are acceptable.
Notes: Any empty sockets must be accounted for by the software when it accesses the physical
pages represented by the empty sockets.
Switch setting of 0 = ON, 1 = OFF. XXX = Don’t care; switch bits not used.
3-5
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