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Theory of Operation
MEMORY CHIP TYPE
The ZT 8825 accepts JEDEC-compatible byte-wide memory devices
of either 28 or 32 pins. All chips in each row of four must be of the
same type (for example, all static RAM in Row A, all EPROM in
Row B) and the same size (all 64K in Row A, all 32K in Row B).
Each row can be selected to be ROM, EPROM, EEPROM, or Flash
or static RAM. Jumper set J1 selects the chip type for Row A and
jumper set J2 selects the chip type for Row B. See page 5-3 for more
information on configuring the board for memory chip type.
MEMORY CHIP SIZE
Switch 1 is a six-segment switch that provides a signal to a pre-
programmed PAL indicating the chip size used in each row. This
allows the PAL to decode the appropriate address bits for the chips
used. Switch 1 segments 6, 5, and 4 select the chip size for Row B
while switch 1 segments 3, 2, and 1 select the chip size for Row A.
Table 3-1 shows the allowable chip size combinations for Row A and
Row B along with the corresponding settings for switch 1. Refer to
page 5-6 for more information on configuring your board for memory
chip size.
3-4
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