Glossary
MCSYNC*
Machine Cycle Sync. STD-80 control signal.
Occurs once during each machine cycle of
the processor. Used on the ZT 8825 to latch
multiplexed memory bits 20-23.
MEMEX
Memory Expansion. STD-80 control signal.
Used on some STD boards to enable 16-bit
memory addressing.
Not used on the
ZT 8825.
MSB
Most Significant Bit.
Page
A 16 Kbyte block of physical memory that
can be mapped in and out of logical memory
by the Expanded Memory Manager.
Page Frame
A 16 Kbyte block of logical memory space
that points to a 16 Kbyte "page" of physical
memory space in expanded memory.
PAL
Programmable Array Logic. Uses a fixed OR
array fed by the output of a programmable
AND array to produce "sum of products"
logic
expressed
in
a
boolean
transfer
function. On the ZT 8825, PALs decode
address bits for an array of memory chip
sizes indicated to it by settings on a six
segment switch.
PBRESET*
Push Button Reset. STD-80 control signal.
This signal is an input line to the system reset
circuit.
PROM disk
See pseudo-disk.
E-3
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