PV152
2-13
PRO1200 CIRCUIT DESCRIPTION
CIRCUIT DESCRIPTION
Pin 17 output is sent to pin 2 of the integrating OP
AMP.
In the locked state of the PLL of TDA2595, this output
is 6 volts.
Any change in frequency is now compensated or cor-
rected by the PLL of TDA2595 and 4046 is switched off.
The above circuit does not require any alignment. It is
completely self-aligning and guarantees a correct lock-
ing to the center of the lock range of the PLL system in
TDA2595.
c) Line oscillator higher than the hor sync:
A similar explanation applies here, although, in this case
the PLL’s output is increasing. Zener diode Z3 does not
limit the voltage because the voltage across it is not 6
volts. Pin 5 ‘follows’ the PLL output.
As there is no coincidence, the other input of the com-
parator goes down resulting in a ‘high’ output for pin 7.
Q9 is turned on and the PLL output can correct the line
oscillator frequency.
VI. Adjustable TOP / BOTTOM BLANKING
(Page 6-12 Sect. D-6)
On the subunit, blanking pulses are generated for an
adjustable blanking of the top and bottom of the pic-
ture by the user.
To achieve a high accuracy, the sawtooth is passed into
a so-called
‘dead band response amplifier’
built up
around an OP AMP in IC8.
The sawtooth is entered at pin 9 of IC8. The output is
inverted and the ramp is steepened at the start and the
end.
Two clipping levels are installed by clamping circuits in
order to obtain a complete feedback between these lev-
els (= center of the screen).
As soon the first clipping level is reached, the output is
invariable. No further change in the output is noticed.
The transformed waveform is now sent to two level de-
tectors in IC9.
The voltage clipping levels of the other inputs of the
comparators are regulated by the potentiometers in IC2
and IC3.
VII. Simulation of the Flyback pulse for the PLL of
TDA2595.
A ‘simulated’ line (flyback) pulse is generated by the
monoflops in IC4. The first monoflop introduces a small
delay for the pulse and the second one determines the
width.
The introduced delay is used to ‘mislead’ the PLL to al-
low a ‘negative’ phase alignment. This phase comparator
(PLL) determines the phase of the squared output at pin
4.
It normally has to compensate for the delays in the power
switching of the deflection circuits. If we mislead this
PLL by giving ‘wrong’ info, the hor. output at pin 4
anticipates the reference (video).
This allows a range for the phase going from a negative
phase shift to a positive one.
VIII. BLANKING - COINCIDENCE
(Page 6-10 Sect. F-9)
In the event of a non - coincidence, transistor Q16
reaches complete saturation since the
COIN NEG
signal
is at a high level.
This results in:
- Led D20 comes on to show the non - coincidence
situation.
- if the strap J5 is in position, transistor Q15 is also
saturated and causes a total blanking of the three crt’s.
TECHNICAL DESCRIPTION “FOCUS - SHIFT”
A. Electromagnetic Focus principle.
In this form of focusing, a strong magnetic field pro-
duced by an electromagnet or a permanent magnet
mounted behind the yoke on the neck of the CRT forces
divergent electrons to take a helical (coil-like) path to
reach the CRT faceplate. The helical path is usually only
one turn long. With the proper magnetic field strength
oppositely divergent electrons will move forward along
coil-like paths that rotate in opposite directions and
meet at the phosphor screen, thereby bringing the elec-
trons together again to form a small spot.
a) At line frequency
(Page 6-18 Sect. C&D-5)
A sawtooth generator is built around Q300 / 301. C302
charges up via the variable (line tracked) current gen-
erator Q300, and discharges via Q301 when a horizontal
pulse is sent to its base. This pulse starts slightly before
