XVME-682 Manual
October, 1989
6.3.4 STATUS___2
This input port is a status port, its bits are defined as follows:
DO-D3 Allows the 80286 to determine where the dual port RAM is mapped on the VMEbus.
D4=0 If the VMEbus requester has ownership of the VMEbus.
D4=1 If not.
D5=0 If VMEbus signal SYSFAIL is asserted.
D5=1 If not.
D6=0 If VMEbus signal ACFAIL is asserted.
D6=1 If not.
D7=0 If the watchdog timer has timed out.
D7=1 If not.
6.3.5 VME_HI_ADD
This output port is used to provide the upper 8 address bits when the VMEbus standard
address space is accessed through the window.
6.3.6 TRIG WDT
This port is used to trigger the watchdog timer. Inputs or outputs to this port will trigger the
watchdog timer. No data is exchanged during these accesses. Refer to Section 6.5.3 for
additional information on the watchdog timer.
6-7
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Содержание XVME-682
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