Xilinx T1, Руководство по установке

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Chapter 5
T1 Skeleton Design
The T1 card skeleton design consists of two separate designs that support the two Xilinx
®
devices (ZU19/Zynq ® Ult™ MPSoC and ZU21/Zynq ® Ult™ RFSoC) on the card.
Each of the designs provides connectivity with the ports on the board from the two devices, and
the ZU21 to the ZU19. There is also a 25G x 4 100G Ethernet connection between the ZU19
and ZU21 devices. These two designs allow testing of the connectivity from the host to the card
and between the two devices to demonstrate that the board is fully functional.
Note: The T1 skeleton design is limited to working only in even-numbered PCIe slots. If you use an odd-
numbered slot, designs can be loaded into the devices, but the tests described in
Chapter 6: Running the
Tests do not run.
T1 Skeleton Design on the ZU19
Zynq Ult MPSoC
The design on the ZU19 Zynq Ult MPSoC has Linux running on the PS Cortex ® -A53
processors and has connections from the PCIe Gen3 x8 from the host to the different parts of
the ZU19. These connections are accomplished through AXI interconnect. These connections are
as follows:
• Processing system and its DDR
• PL DDR through a MIG DDR controller
• 100G MAC
• Two 25G MAC connections
The block diagram below shows the connections.
Chapter 5: T1 Skeleton Design
UG1518 (v1.0) December 17, 2021 www.xilinx.com
T1 Telco Accelerator Card Installation Guide 16
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