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Table 16: Receiver Core Configuration (0x04) (cont'd)

Bit

Default

Value

Access

Type

Description

7:1

RSVD

Is I2S Master: Indicates if the core has been generated as an I2S Master or Slave.
1 = I2S Master

Control Register (0x08)

This register provides capability to enable/disable the core.

Table 17: Receiver Control Register (0×08)

Bit

Default

Value

Access

Type

Description

31:17

Reserved

R/W

Latch AES Channel Status: Program this bit to latch the AES Channel Status bits

from registers. This latched value is then put onto the AXIS interface. This

15:1

Reserved

0x0

R/W

Enable: Setting this bit to ‘1’ enables the core operations. Setting this bit to ‘0’

disables the core operations

Interrupt Control Register (0x10)

This registers determines the interrupts sources in the Interrupt Status register that are allowed
to generate an interrupt. Writing a ‘1’ to a bit enables the corresponding interrupt.

Table 18: Receiver Interrupt Control Register (0×10)

Bit

Default

Value

Access

Type

Description

R/W

Global Interrupt Enable: Enable Global Interrupt

30:2

Reserved

R/W

Overflow Interrupt Enable: Enable overflow interrupt

R/W

AES Block Completed Interrupt enable: Enable AES Block Completed interrupt

Interrupt Status (0x14)

This register returns the status of the Interrupt bits.

Chapter 3: Product Specification

PG308 (v1.0) April 4, 2018

www.xilinx.com

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I2S Transmitter and I2S Receiver

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Содержание I2S

Страница 1: ...I2S Transmitter and I2S Receiver v1 0 LogiCORE IP Product Guide Vivado Design Suite PG308 v1 0 April 4 2018...

Страница 2: ...Register Space 16 Chapter 4 Designing with the Core 22 General Design Guidelines 23 Clocking 24 Resets 24 Programmimg Sequence 24 Interrupts 25 Audio AXIS Interface 25 Chapter 5 Design Flow Steps 27 C...

Страница 3: ...e Debug 37 Appendix B Additional Resources and Legal Notices 38 Xilinx Resources 38 Documentation Navigator and Design Hubs 38 References 39 Training Resources 39 Revision History 39 Please Read Impor...

Страница 4: ...xtraction insertion IP Facts LogiCORE IP Facts Table Core Specifics Supported Device Family1 UltraScale UltraScale Zynq 7000 SoC 7 series Zynq UltraScale MPSoC Supported User Interfaces AXI4 Lite AXI4...

Страница 5: ...of supported devices see the Vivado IP catalog 2 Standalone driver details can be found in the software development kit SDK directory install_directory SDK release data embeddedsw doc xilinx_drivers...

Страница 6: ...I2S Tramsmitter and I2S Receiver IPs can be used to develop audio solution using I2S ADC DACs These IPs are typically used with video connectivity IPs such as HDMI and Display Port to play or insert...

Страница 7: ...es and tools contact your local Xilinx sales representative License Checkers If the IP requires a license key the key must be verified The Vivado design tools have several license checkpoints for gati...

Страница 8: ...asy to configure with minimal register programming Figure 1 TX Audio Sampling AES3 Audio Decoder FIFO Register Interface I2S TX I2S Timing Gen Sdata 3 0 SCK LRCLK AXIS Audio AES3 s_axis_aud_aclk aud_m...

Страница 9: ...rce use visit the Performance and Resource Use web page for transmitter and Performance and Resource Use web page for receiver Resource Use For full details about performance and resource use visit th...

Страница 10: ...configured as Slave Sclk_in I SCLK Input SCK Clock Available when core is configured as Slave sdata_0_out O SDATA0 I2S Serial Data out sdata_1_out O SDATA1 I2S Serial Data out Available when number o...

Страница 11: ...ite access register is updated by the 32 bit AXI Write Data _wdata signal and is not impacted by the AXI Write Data Strobe _wstrb signal For a Write both the AXI Write Address Valid _awvalid and AXI W...

Страница 12: ...lue Access Type Description 31 16 0x1 RO Major Revision This is the IP major revision value For example if the IP version is 1 2 then this will return a value of 1 15 0 0x0 RO Minor Revision This is t...

Страница 13: ...rupt 1 0 R W AES Block Sync Error Interrupt enable Enable AES block sync interrupt 0 0 R W AES Block Completed Interrupt enable Enable AES Block Completed interrupt Interrupt Status 0x14 This register...

Страница 14: ...audio received on channels 2 3 can be routed to output on any of the four I2S ports Similarly audio received on channels 0 1 can be routed to all of the four I2S ports Table 9 Transmitter Channel 0 1...

Страница 15: ...Channel 4 5 Control 0x38 Bit Default Value Access Type Description 31 3 Reserved 2 0 0x3 R W Channel Mux Value Specify a value to Multiplex the audio channel output 0x0 Output on I2S channel 2 is dis...

Страница 16: ...restart the process of accumulating the channel status and would result in the AES Channel Status Updated interrupt The 6 registers give the value in order of LSB to MSB The register 0x50 returns bit...

Страница 17: ...tus Core Version 0x00 This register returns the major and minor versions of the IP core Table 15 Receiver Core Version 0x00 Bit Default Value Access Type Description 31 16 0x1 RO Major Revision This i...

Страница 18: ...to 1 enables the core operations Setting this bit to 0 disables the core operations Interrupt Control Register 0x10 This registers determines the interrupts sources in the Interrupt Status register t...

Страница 19: ...divider should be such that the following criteria is satisfied MCLK SCLK Divider_value 2 This register has to be programmed when core is configured as I2S Master Channel 0 1 Control 0x30 The IP prov...

Страница 20: ...dio received on I2S Channel 0 can be routed to any of the 8 audio channels Similarly audio received on one I2S channel can be routed to all of the 8 audio channels Table 23 Receiver Channel 4 5 Contro...

Страница 21: ...r registers should be unique and different The IP may not behave as expected if the same value is programmed in all the registers AES Channel Status 0x50 0x64 These six registers together allow the us...

Страница 22: ...RX Audio Source I2S TX Audio Sink I2S RX External I2S DAC External I2S ADC To Speakers or amp Line in AXIS AXIS MCLK X20719 042318 The I2S IPs typically interface with the external ADC DAC which faci...

Страница 23: ...This means that all inputs and outputs from the user application should come from or connect to a flip flop While registering signals might not be possible for all paths it simplifies timing analysis...

Страница 24: ...ets the register interface and puts all the registers in their default state The aud_mrst an Active High reset resets the audio domain while the s_axis_aud_aresetn resets the AXIS domain After a reset...

Страница 25: ...pects the channels in sequential order If the channel data is not in order then the I2S Transmitter would assert underflow or block sync error Figure 4 Audio AXIS Interface CLK TDATA 31 0 TVALID TREAD...

Страница 26: ...ion 0001 Start of Audio Block Channel 0 Audio sample 0010 Channel 0 2 4 6 Audio data 0011 Channel 1 3 5 7 Audio data Chapter 4 Designing with the Core PG308 v1 0 April 4 2018 www xilinx com placeholde...

Страница 27: ...ng project or create a new project using the Vivado design tools 2 Open the IP catalog and navigate to the taxonomies 3 Double click on either I2S Receiver or Transmitter to bring up the customize IP...

Страница 28: ...I2S Receiver Customize IP Figure 5 I2S Receiver Configuration Tab Chapter 5 Design Flow Steps PG308 v1 0 April 4 2018 www xilinx com placeholder text I2S Transmitter and I2S Receiver 28 Send Feedback...

Страница 29: ...ues are 2 4 6 and 8 I2S Data Width Specify the I2S data width Allowed values are 16 and 24 FIFO Depth Specify the depth of the FIFO Allowed values are 64 128 256 512 and 1024 In case of I2S Transmitte...

Страница 30: ...256 512 1024 Enable FIFO Count C_ENABLE_FIFO_COUNT False True False Output Generation For details see the Vivado Design Suite User Guide Designing with IP UG896 Constraining the Core Required Constra...

Страница 31: ...is not applicable for this IP core Simulation For comprehensive information about Vivado simulation components as well as information about using supported third party tools see the Vivado Design Sui...

Страница 32: ...I4 Lite and AXI4 Stream interfaces of the DUT Clock generator A clocking wizard is used to generate the clocks for the example design It generates the aud_clk AXI4 Lite clock and the AXI4 Stream clock...

Страница 33: ...roject with the name _ex0 is created and the files are delivered in that directory This directory and its subdirectories contain all the source files that are required to create the AXI MCDMA controll...

Страница 34: ...est bench for example design The top level test bench feeds a clock input AXIS data to the exdes The TB also checks the received AXIS data AXIS Data Generator This module generates the AXIS Audio traf...

Страница 35: ...level Finding Help on Xilinx com To help in the design and debug process when using the core the Xilinx Support web page contains key resources such as product documentation release notes answer reco...

Страница 36: ...r target the results Master Answer Record for the Core For I2S Receiver see Xilinx Answer 70288 For I2S Transmitter see Xilinx Answer 70699 Technical Support Xilinx provides technical support in the X...

Страница 37: ...e ADC DAC CODEC is in Slave mode The I2S IPs operate as Masters The I2S IPs only support 16 or 24 bit I2S mode only 2 Audio has a lot of noise Ensure that DAC ADC CODEC are configured for the same dat...

Страница 38: ...ct Start All Programs Xilinx Design Tools DocNav At the Linux command prompt enter docnav Xilinx Design Hubs provide links to documentation organized by design tasks and other topics which you can use...

Страница 39: ...ite User Guide Programming and Debugging UG908 6 ISE to Vivado Design Suite Migration Guide UG911 7 Vivado Design Suite User Guide Implementation UG904 Training Resources 1 Vivado Design Suite Hands o...

Страница 40: ...r to Xilinx s Terms of Sale which can be viewed at https www xilinx com legal htm tos IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx Xilinx produc...

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