Xembedded XVME-689-VR7, Руководство пользователя

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Programming
4-8
High Byte
Low Byte
Low Byte
High Byte
INTEL MOTOROLA
Address
M
M+1
M+2
M+3
i i
i i
Figure 4-1 Byte Ordering Schemes
Note
The two architectures differ only in the way in which they store data into
memory, not in the way in which they place data on the shared data bus.
The XVME 689-VR7 contains a Universe chip that performs address-invariant translation between
the PCI bus (Intel architecture) and the VMEbus (Motorola architecture), and byte-swapping
hardware to reverse the Universe chip byte-lane swapping. (Contact Tundra at www.tundra.com for a
PDF version of the Universe manual.) Figure 4-2 shows address-invariant translation between a PCI
bus and a VMEbus.
Figure 4-2 Address-Invariant Translation
Notice that the internal data storage scheme for the PCI (Intel) bus is different from that of the VME
(Motorola) bus. For example, the byte
78
(the least significant byte) is stored at location M on the PCI
machine while the byte
78
is stored at the location
M+3
on the VMEbus machine. Therefore, the data
bus connections between the architectures must be mapped correctly.