Xembedded XPMC-9100, Руководство пользователя

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Introduction
XCPC-9100 as the System controller and Peripheral
The XCPC-9100 utilizes PLX PCI6540 chip for its interface to the cPCI back plane.
The chip is a high performance asynchronous 133MHz, 64-bit PCI-X to PCI-X
bridge. When the module is in the system controller slot the device runs in
transparent P2P bridge. This allows the PrPMC on the Carrier to detect all the
devices that on the cPCI chassis.
When the module is in the Peripheral slot, the device run in non-transparent mode.
The primary side of the device is the Carrier and secondary side of the P2P is
connected to the cPCI back plane. The Primary side which hosts the PrPMC/PMC
can run at a different speed vs. the cPCI backplane. This allows the two clock
domain to be asynchronous. In this mode the PrPMC slot which is configured to be
in the monarch mode (setting is done via the P5 jumper), will configure the Carrier
side. The secondary side of the bridge is configured via the cPCI chassis system
controller.
Carrier Interface to the cPCI back plane
In the system controller slot the carrier driver the clock and all the requests/grants to
the each of the cPCI slots. The Carrier further routes all the cPCI Interrupts to the
Carrier PrPMC. The Carrier can run in cPCI chassis that have +5V or +3.3V PCI
signaling. It can also run in PCI-X cPCI chassis.
In the Peripheral slot the bridge is running in non-transparent mode. This allows the
system controller on the cPCI to configure the secondary side, however the primary
side is configured by the Carrier PrPMC.
In non-transparent mode there are several ways to allow the boot sequencing go
through. First the system controller and the Carrier can boot simultaneously (no
priority is given). The Carrier requests for 16MB window on it’s BAR registers by
default (P5 header, remove pin 1-2 and 11-12). In the second case the Carrier must
boots first and before the system controller is booted. Installing jumpers on P5 pins
1-2 and 11-12 lets the bridge issue PCI retries on the bus till the Carrier PrPMC
release the bridge. Consult the PLX 6540 data book on the registers settings.
XCPC-9100 as the system controller
As the system controller the XCP-9100 will try to operate the PCI in PCI-X mode at
66MHz (if the chassis has the capability). The PCI clock will automatically adjust,
unless the P5 pin 3-4 or 9-10 is set. When jumper 3-4 is installed the cPCI will clock
at max 66MHz in PCI mode. If jumper 9-10 is installed the cPCI bus is forced to run
at 33MHz. The slowest peripheral device on the cPCI will dictate the speed of the
PCI bus. The clock is automatically adjusted unless the jumpers are set to override.
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