Xembedded XPMC-9100, Руководство пользователя

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Introduction
Main Features
Dual 10/100/1000-BaseTX Ethernet to cPCI J3
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The XCPC-9100 has two GbE routed to J3 connector interface per PICMIG 2.16 specification from the
on-board switch. The transceivers are fully integrated 10/100/1000BaseT Gigabit Ethernet transceivers.
The 10/100/1000-BaseTX Gigabit Ethernet transceivers feature:
•
Fully integrated 10BaseT/100BaseTX and 1000BaseT Gigabit Ethernet
•
Fully compliant with IEEE 802.3, 802.3u and 802.3ab standards
•
Support for jumbo packets up to 9Kbytes
Dual Port 10/100/1000-BaseTX Ethernet to each PMC site
The XCPC-9100 has a dual port 10/100/1000 Mbit from the on-board switch which
is routed to the PMC J4 (user defined pins). Alternately these signals are routed
through mechanical switches which allow user defined pins to also go to the J5
Connector (for rear transition module access).
Dual 10/100/1000-BaseTX Ethernet to Front
The XCPCI-9100 has dual port 10/100/1000-BaseTX routed to the front. This allows
the module to run as stand alone without having external switches or a 2.16 switch
Fabric in the system.
Layer Two Semi-Managed Switch
The on board switch Fabric is capable of layer two management. Only certain
features are incorporated. The switch can be configured to support Port VLAN
programming, see Chapter 3 for more information. Contact Xembedded for other
types of custom re-configuration.
IPMI FRU
The XCPC-9100 uses the NXP LPC2138 micro controller on board for the FRU
information. The micro controller communicates with the BMC via the I2C bus and
follows the cPCI specification. See appendix A for the layout of the FRU file. The
Micro controller also communicates with the GbE switch for it’s management
portion.
NOTE : Please contact Xembedded for the list of features for the Layer two Managed
switch.
PCI Bus interface
The XCPC-9100 uses the PLX-6540 bridge for the PCI bus interface to the cPCI bus.
The bridge has the following features:
•
PCI R2.3 capable
•
PICMG 2.1 Hot swappable
•
PCIX 64-bit, 33MHz to 133Mhz PCI clock speed
•
Asynchronous operation across the Primary and Secondary (That is the
Primary and Secondary can run at two different speed)
•
10KB FIFO
•
As the system controller runs in Transparent mode and as a peripheral runs
in non-transparent mode
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