WinSystems PCM-A/D-12 Скачать руководство пользователя страница 62

Страница: 62 / 76

ADS7807

Figure 15 shows another interface between the ADS7807
and a QSPI equipped microcontroller which allows the
microcontroller to give the convert pulses while also allow-
ing multiple peripherals to be connected to the serial bus.
This interface and the following discussion assume a master
clock for the QSPI interface of 16.78MHz. Notice that the
serial data input of the microcontroller is tied to the MSB
(D7) of the ADS7807 instead of the serial output (SDATA).
Using D7 instead of the serial port offers tri-state capability
which allows other peripherals to be connected to the MISO
pin. When communication is desired with those peripherals,
PCS0 and PCS1 should be left HIGH; that will keep D7 tri-
stated.

In this configuration, the QSPI interface is actually set to do
two different serial transfers. The first, an eight bit transfer,
causes PCS0 (R/C) and PCS1 (CS) to go LOW starting a
conversion. The second, a sixteen bit transfer, causes only
PCS1 (CS) to go LOW. This is when the valid data will be
transferred.

For both transfers, the DT register (delay after transfer) is
used to cause a 19

s delay. The interface is also set up to

wrap to the beginning of the queue. In this manner, the QSPI
is a state machine which generates the appropriate timing for
the ADS7807. This timing is thus locked to the crystal based
timing of the microcontroller and not interrupt driven. So,
this interface is appropriate for both AC and DC measure-
ments.

For the fastest conversion rate, the baud rate should be set to
two (4.19MHz SCK), DT set to ten, the first serial transfer
set to eight bits, the second set to 16 bits, and DSCK
disabled (in the command control byte). This will allow for
a 23kHz maximum conversion rate. For slower rates, DT
should be increased. Do not slow SCK as this may increase
the chance of affecting the conversion results or accidently

initiating a second conversion during the first eight bit
transfer.

In addition, CPOL and CPHA should be set to zero (SCK
normally LOW and data captured on the rising edge). The
command control byte for the eight bit transfer should be set
to 20H and for the sixteen bit transfer to 61H.

SPI INTERFACE

The SPI interface is generally only capable of 8-bit data
transfers. For some microcontrollers with SPI interfaces, it
might be possible to receive data in a similar manner as
shown for the QSPI interface in Figure 14. The
microcontroller will need to fetch the 8 most significant bits
before the contents are overwritten by the least significant
bits.

A modified version of the QSPI interface shown in Figure 15
might be possible. For most microcontrollers with SPI inter-
face, the automatic generation of the start-of-conversion
pulse will be impossible and will have to be done with
software. This will limit the interface to ‘DC’ applications
due to the insufficient jitter performance of the convert pulse
itself.

DSP56000 INTERFACING

The DSP56000 serial interface has SPI compatibility mode
with some enhancements. Figure 16 shows an interface
between the ADS7807 and the DSP56000 which is very
similar to the QSPI interface seen in Figure 14. As men-
tioned in the QSPI section, the DSP56000 must be pro-
grammed to enable the interface when a LOW to HIGH
transition on SC1 is observed (BUSY going HIGH at the end
of conversion).

The DSP56000 can also provide the convert pulse by includ-
ing a monostable multi-vibrator as seen in Figure 17. The
receive and transmit sections of the interface are decoupled
(asynchronous mode) and the transmit section is set to
generate a word length frame sync every other transmit
frame (frame rate divider set to two). The prescale modulus
should be set to three.

FIGURE 15. QSPI Interface to the ADS7807. Processor

Initiates Conversions.

R/C

DATACLK

D7 (MSB)

BYTE

ADS7807

PCS0

PCS1

SCK

MISO

QSPI