WinSystems PCM-A/D-12, Руководство по эксплуатации

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12
®
ADS7806
FIGURE 6. Conversion and Read Timing with External Clock (EXT/INT tied HIGH) Read During a Conversion.
EXTERNAL DATA CLOCK
(After a Conversion)
After conversion ‘n’ is completed and the output registers
have been updated, BUSY (pin 24) will go HIGH. With CS
LOW and R/C HIGH, valid data from conversion ‘n’ will be
output on SDATA (pin 19) synchronized to the external data
clock input on DATACLK (pin 18). The MSB will be valid
on the first falling edge and the second rising edge of the
external data clock. The LSB will be valid on the 12th falling
edge and 13th rising edge of the data clock. TAG (pin 20)
will input a bit of data for every external clock pulse. The
first bit input on TAG will be valid on SDATA on the 13th
falling edge and the 14th rising edge of DATACLK; the
second input bit will be valid on the 14th falling edge and the
15th rising edge, etc. With a continuous data clock, TAG
data will be output on SDATA until the internal output
registers are updated with the results from the next conver-
sion. Refer to Table VI and Figure 5.
EXTERNAL DATA CLOCK
(During a Conversion)
After conversion ‘n’ has been initiated, valid data from
conversion ‘n-1’ can be read and will be valid up to 12
µ
s
after the start of conversion ‘n’. Do not attempt to clock out
data from 12
µ
s after the start of conversion ‘n’ until BUSY
(pin 24) rises; this will result in data loss. NOTE: For the
best possible performance when using an external data
clock, data should not be clocked out during a conversion.
The switching noise of the asynchronous data clock can
cause digital feedthrough degrading the converter’s perfor-
mance. Refer to Table VI and Figure 6.
TAG FEATURE
TAG (Pin 20) inputs serial data synchronized to the external
or internal data clock.
When using an external data clock, the serial bit stream input
on TAG will follow the LSB output on SDATA until the
internal output register is updated with new conversion
results. See Table VI and Figures 5 and 6.
The logic level input on TAG for the first rising edge of the
internal data clock will be valid on SDATA after all 12 bits
of valid data have been output.
INPUT RANGES
The ADS7806 offers three input ranges: standard
±
10V and
0-5V, and a 0-4V range for complete, single supply systems.
Figures 7a and 7b show the necessary circuit connections for
implementing each input range and optional offset and gain
adjust circuitry. Offset and full scale error
(1)
specifications
are tested and guaranteed with the fixed resistors shown in
Figure 7b. Adjustments for offset and gain are described in
the Calibration section of this data sheet.
The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors com-
pensate for this adjustment and can be left out if the offset
and gain will be corrected in software (refer to the Calibra-
tion section).
The input impedance, summarized in Table II, results from the
combination of the internal resistor network shown on the
front page of the product data sheet and the external resistors
NOTE: (1) Full scale error includes offset and gain errors measured at both
+FS and –FS.
EXTERNAL
DATACLK
CS
Bit 11 (MSB)
R/C
BUSY
DATA
TAG
Bit 0 (LSB) Tag 0 Tag 1
Tag 1 Tag 12
Tag 13 Tag 14
Tag 0
t
20
t
21
t
1
t
11
t
3
t
17
t
18
t
19
t
22
t
20