Winbond W83627DHG, Руководство пользователя

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W83627DHG
Publication Release Date: Aug, 22, 2007
-151- Version 1.4
12.3.1 ECP Register and Bit Map
The next two tables list the registers used in the ECP mode and provide a bit map of the parallel port
and ECP registers.
NAME ADDRESS I/O ECP MODES FUNCTION
data Base+000h R/W 000-001 Data Register
ecpAFifo Base+000h R/W 011 ECP FIFO (Address)
dsr Base+001h R All Status Register
dcr Base+002h R/W All Control Register
cFifo Base+400h R/W 010 Parallel Port Data FIFO
ecpDFifo Base+400h R/W 011 ECP FIFO (DATA)
tFifo Base+400h R/W 110 Test FIFO
cnfgA Base+400h R 111 Configuration Register A
cnfgB Base+401h R/W 111 Configuration Register B
ecr Base+402h R/W All Extended Control Register
Note:
The base addresses are specified by CR60 and 61, which are determined by the configuration register or the hardware
setting.
D7 D6 D5 D4 D3 D2 D1 D0 NOTE
Data PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
ecpAFifo Addr/RLE Address or RLE field 2
Dsr nBusy nAck PError Select nFault 1 1 1 1
Dcr 1 1 Directio ackIntEn SelectIn nInit autofd strobe 1
cFifo Parallel Port Data FIFO 2
ecpDFifo ECP Data FIFO 2
tFifo Test FIFO 2
cnfgA 0 0 0 1 0 0 0 0
cnfgB compress intrValue 1 1 1 1 1 1
Ecr MODE nErrIntrEn dmaEn serviceIntr full empty
Notes:
1. These registers are available in all modes.
2. All FIFOs use one common 16-byte FIFO.
Each register (or pair of registers, in some cases) is discussed below.