Vig395P Motherboard Manual
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Advanced Chipset Control
Access the submenu to make changes to the following settings.
CAUTION!!
Take Caution when changing the Advanced settings. Incorrect values entered
may cause system malfunction. Also, a very high DRAM frequency or incorrect
DRAM timing may cause system instability. When this occurs, revert to the
default setting.
SERR Signal Condition
This setting specifies the ECC Error conditions that an SERR# is to be asserted.
The options are None,
Single Bit
, Multiple Bit, and Both.
4GB PCI Hole Granularity
This feature allows you to select the granularity of PCI hole for PCI slots. If MTRRs are
not enough, this option may be used to reduce MTRR occupation. The options are:
256
MB
, 512 MB, 1GB and 2GB.
Memory Branch Mode
This option determines how the memory branch operates. System address space can
either be interleaved between two channels or Sequential from one channel to another.
Single Channel 0 allows a single DIMM population during system manufacturing. The
options are
Interleave
, Mirroring, Sequential and Single Channel 0.
Branch 0 Rank Interleaving & Sparing
Select enable to enable the functions of Memory Interleaving and Memory Sparing for
Branch 0 Rank. The options for Memory Interleaving are 1:1, 2:1 and
4:1
. The options
for Sparing are Enabled and
Disabled
.
Branch 1 Rank Interleaving & Sparing
Select enable to enable the functions of Memory Interleaving and Memory Sparing for
Branch 1 Rank. The options for Memory Interleaving are 1:1, 2:1 and
4:1
. The options
for Sparing are Enabled and
Disabled
.
Enhanced x8 Detection
Select
Enabled
to enable Enhanced x8 DRAM UC Error Detection. The options are
Disabled and
Enabled
.
Crystal Beach Features
This feature cooperates with Intel I/O AT (Acceleration Technology) to accelerate the
performance of TOE devices. (*Note: A TOE device is a specialized, dedicated
processor that is installed on an add-on card or a network card to handle some or all
packet processing of this add-on card. For this Motherboard, the TOE device is built
inside the ESB 2 South Bridge chip.) The options are
Enabled
and Disabled.
