Unigraf UCD-240, Руководство пользователя

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UCD Console for UCD-340 User Manual | Unigraf Oy
32.
After the re-plug event, Ra is connected to CC2 and Rd is connected to CC1. DUT is
expected to have Rp, or a current source applied to both CC1 and CC2 lines. The
impedance of DUT’s Rp resistor, or current source must be adjusted so that the voltage
drop on Rd resistor in TE is within one of the voltage ranges defined by the provided
parameters.
TE will measure the voltage drop on Rp.
Once DUT has started to provide Vconn on CC2, TE will measure the voltage present on
CC2. After that TE will do a cable-flip and repeat the steps as above.
For a PASS result, measured values from CC1, CC2 and Vconn must be within ranges
defined by the provided parameters.
Note Configuration items for this test should be programmed with averaged values from several
“golden sample” DUT’s.
Important In order to run this test with UCD-340, Unigraf Electrical Test Cable must be used and
Electrical Testing feature enabled with a corresponding license.
Parameters in use
 Test timeout (default 5 000 ms)
 R-plug duration (default 1 500 ms)
 DUT attach timeout (default 10 000 ms)
 CC low voltage limit for default current (0.5/0.9A) (default 261 mV)
 CC high voltage limit for default current (0.5/0.9A) (default 588 mV)
 CC low voltage limit for 1.5A current (default 675 mV)

CC high voltage limit for 1.5A current (default 1 189 mV)
 CC low voltage limit for 3A current (default 1 238 mV)
 CC high voltage limit for 3A current (default 2 181 mV)
 Vconn low voltage limit (4 750 mV)
 Vconn high voltage limit (5 500 mV)
AUX (SBU) Lines Test
This test verifies operation of SBU lines for short-circuit and open-circuit failures and that
hardware directly related to SBU lines is working properly. During the test the TE will
operate as Type-C UFP device. For this test, DUT must support DisplayPort Alternate
Mode.
In the start of the test TE temporarily disconnects the CC lines to simulate a re-plug event
and waits for DUT to enter DP Alternate mode.
Once DUT has entered the DP alternate mode, TE will measure voltage levels on SBU1
(AUX+) and SBU2 (AUX-) lines. Please notice that if TE is acting as DP Sink, it will de-
assert HPD signal to keep AUX bus at IDLE state during the voltage measurements.
Once the voltages are measured, TE will do a cable-flip and repeat the steps as above.
For a PASS result, the measured voltages must be within the ranges defined by the
provided parameters.
Note Parameters for this test should be programmed with averaged values from several “golden
sample” DUT’s.