Ublox SARA-N210, Руководство по системной интеграции

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SARA-N2 series - System Integration Manual
UBX-17005143 - R06 System description Page 8 of 82
1.3 Pin-out
Table 3 lists the pin-out of the SARA-N2 series modules, with pins grouped by function.
Function Pin Name Pin No I/O Description Remarks
Power VCC 51, 52, 53 I Module supply
input
All VCC pins must be connected to external supply.
VCC supply circuit affects the RF performance and
compliance of the device integrating the module with
applicable required certification schemes.
See section
1.5.1 for description and requirements.
See section 2.2.1 for external circuit design-in.
GND 1, 3, 5, 14, 20-22,
30, 32, 43, 50, 54,
55, 57-61, 63-96 N/A Ground GND pins are internally connected to each other.
External ground connection affects the RF and thermal
performance of the device.
V_INT 4 O
Generic Digital
Interfaces supply
output
V_INT = 1.8 V (typical) supply output, generated by
internal linear LDO regulator when the radio is on.
Provide a test point on this pin for diagnostic purpose.
See section
1.5.2 for functional description.
See section 2.2.2 for external circuit design-in.
System RESET_N 18 I External reset
input
Internal 78 k  pull-up to VCC.
Provide a test point on this pin for diagnostic purpose.
See section
1.6.3 for functional description.
See section 2.3.1 for external circuit design-in.
Antenna ANT 56 I/O RF
input/output
for antenna
50  nominal characteristic impedance.
Antenna circuit affects the RF performance and
compliance of the device integrating the module with
applicable required certification schemes.
See section
1.7 for description and requirements.
See section 2.4 for external circuit design-in.
ANT_DET 62 I Input for antenna
detection ANT_DET not supported by "02" product versions.
ADC input for antenna detection function.
See section
1.7.2 for functional description.
See section 2.4.2 for external circuit design-in.
SIM VSIM 41 O SIM supply output VSIM = 1.80 V (typical).
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_IO 39 I/O SIM data Internal 4.7 k  pull-up to VSIM.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_CLK 38 O SIM clock Clock for external SIM, operating at VSIM voltage level.
See section
1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_RST 40 O SIM reset
Reset for external SIM, operating at VSIM voltage level.
See section
1.8 for functional description.
See section 2.5 for external circuit design-in.