Ublox SARA-N210, Руководство по системной интеграции

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SARA-N2 series - System Integration Manual
UBX-17005143 - R06 System description Page 17 of 82
1.7.2 Antenna detection interface (ANT_DET)
☞
Antenna detection interface is not supported in the "02" version of the product.
The ANT_DET pin is an Analog to Digital Converter (ADC) input used to sense the antenna presence
evaluating the resistance from the ANT pin to GND by means of an external antenna detection circuit
implemented on the application board. This optional functionality can be managed by dedicated AT
command (for more details see the SARA-N2 series AT Commands Manual
[3] ).
1.8 SIM interface
SARA-N2 series modules provide a high-speed SIM/ME interface working at 1.8 V, which is available
to connect an external SIM / UICC.
The VSIM supply output provides internal short circuit protection to limit start-up current and protect
the external SIM / UICC to short circuits.
1.9 Serial interfaces
SARA-N2 series modules provide the following serial communication interfaces:
 UART interface: 5-wire unbalanced asynchronous serial interface, operating at VCC voltage level
(~3.6 V), supporting (see
1.9.1 ):
o
AT command
o
FW upgrades by means of the FOAT feature
o
FW upgrades by means of the dedicated tool
 Auxiliary UART interface: 2-wire unbalanced asynchronous serial interface, operating at V_INT
level (1.8 V), supporting (see
1.9.2 ):
o
Trace log capture (diagnostic purpose)

DDC interface
1
: I2C-bus compatible interface, operating at V_INT level (1.8 V), supporting (see
1.9.3 ):
o
Communication with external chips and sensors
o
Communication with external u-blox GNSS chips / modules
1.9.1 Asynchronous serial interface (UART)
1.9.1.1 UART features
The UART interface is a 5-wire unbalanced asynchronous serial interface, supporting:
 AT command
 FW upgrades by means of the FOAT feature
 FW upgrades by means of the dedicated tool
The main characteristics of the interface are the following:
 Serial port with RS-232 functionality working at the VCC voltage domain (0 V for low data bit or
ON state and ~3.6 V, i.e. VCC, for high data bit or OFF state)
 Data lines (RXD as module data output, TXD as module data input)
 Hardware flow control lines (CTS as module output, RTS as module input)
 Default baud rate: 9600 b/s (4800, 57600 and 115200 b/s baud rates are also supported)
 Fixed frame format: 8N1 (8 data bits, No parity, 1 stop bit)
1 Not supported on “02” product version