Ublox SARA-N210, Руководство по системной интеграции

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SARA-N2 series - System Integration Manual
UBX-17005143 - R06 System description Page 7 of 82
Table 2 summarizes cellular radio access technology characteristics of SARA-N2 series modules.
Item SARA-N200 SARA-N201 SARA-N210 SARA-N211 SARA-N280
NB-IoT protocol stack 3GPP Release 13 3GPP Release 13 3GPP Release 13 3GPP Release 13 3GPP Release 13
Operating band Band 8 (900 MHz) Band 5 (850 MHz) Band 20 (800 MHz) Band 8 (900 MHz),
Band 20 (800 MHz)
Band 28 (700 MHz)
Deployment mode In-Band
Guard-Band
Standalone In-Band
Guard-Band
Standalone In-Band
Guard-Band
Standalone In-Band
Guard-Band
Standalone In-Band
Guard-Band
Standalone
Power Class Class 3 (23 dBm) Class 3 (23 dBm) Class 3 (23 dBm) Class 3 (23 dBm) Class 3 (23 dBm)
Data rate LTE category NB1:
Up to 31.25 kb/s UL
Up to 27.2 kb/s DL LTE category NB1:
Up to 31.25 kb/s UL
Up to 27.2 kb/s DL LTE category NB1:
Up to 31.25 kb/s UL
Up to 27.2 kb/s DL LTE category NB1:
Up to 31.25 kb/s UL
Up to 27.2 kb/s DL LTE category NB1:
Up to 31.25 kb/s UL
Up to 27.2 kb/s DL
Table 2: SARA-N2 series NB-IoT characteristics summary
1.2 Architecture
Figure 1 summarizes the architecture of SARA-N2 series modules, describing the internal blocks of
the modules, consisting of the RF, Baseband and Power Management main sections, and the available
interfaces.
Memory
V_INT
38.4 MHz
32.768 kHz
RF
Transceiver
Power
Management
Baseband
ANT
SAW
Filter
Switch
PA
VCC (Supply)
DDC (I 2 C)
UART
SIM
Secondary UART
RESET_N
GPIO
Antenna detection
Figure 1: SARA-N2 series modules block diagram
The RF section is composed of the following main elements:
 LTE Power Amplifier, which amplifies the signals modulated by the RF transceiver

RF switches, which connect the antenna input/output pin (ANT) of the module to the suitable
RX/TX path
 RX low-loss SAW filters
 38.4 MHz crystal oscillator for the clock reference in active-mode and connected-mode
The Baseband and Power Management section is composed of the following main elements:

Baseband processor
 Flash memory
 Voltage regulators to derive all the system supply voltages from the module supply VCC
 Circuit for the RTC clock reference in low power deep-sleep