SARA-G450 - System integration manual
UBX-18046432 - R08
Design-in
Page 63 of 143
C1-Public
2.2.1.5
Guidelines for VCC supply circuit design using a primary battery
The characteristics of a primary (non-rechargeable) battery connected to the VCC pins should meet
the following prerequisites to comply with the module VCC requirements summarized in
Maximum pulse and DC discharge current: the non-rechargeable battery with its output circuit
must be capable of delivering to VCC pins the specified maximum peak / pulse current with
1/8 duty cycle, and a DC current greater than the module maximum average current consumption
(see the SARA-G450 data sheet
). The maximum pulse and the maximum DC discharge current
is not always detailed in battery data sheets, but the maximum DC discharge current is typically
almost equal to the battery capacity in Amp-hours divided by 1 hour.
DC series resistance: the non-rechargeable battery with its output circuit must be capable of
avoiding a VCC voltage drop greater than 400 mV during transmit bursts.
2.2.1.6
Additional guidelines for VCC supply circuit design
To reduce voltage drops, use a low impedance power source. The resistance of the power supply lines
(connected to the VCC and GND pins of the module) on the application board and battery pack should
also be considered and minimized: cabling and routing must be as short as possible to minimize power
losses.
Three pins are allocated for VCC supply. Another fifty-one pins are designated for GND connection. It
is highly recommended to properly connect all the VCC pins and all the GND pins to supply the module,
in order to minimize series resistance losses.
To avoid voltage drop undershoot and overshoot at the start and end of a transmit burst during a
single-slot 2G transmission (when current consumption on the VCC supply can rise up to the
maximum peak / pulse current specified in the SARA-G450 data sheet
), place a bypass capacitor
with large capacitance (more than 100
µ
F) and low ESR near the VCC pins, for example:
330
µ
F capacitance, 45 m
Ω
ESR (e.g. KEMET T520D337M006ATE045, tantalum capacitor)
To reduce voltage ripple and noise, especially if the application device integrates an internal antenna,
place the following bypass capacitors near the VCC pins:
100 nF capacitor (e.g. Murata GRM155R61C104K) to filter digital logic noise from clocks and data
sources
10 nF capacitor (e.g. Murata GRM155R71C103K) to filter digital logic noise from clocks and data
sources
56 pF capacitor with Self-Resonant Frequency in 800/900 MHz range (e.g. Murata
GRM1555C1E560J) to filter transmission EMI in the GSM/EGSM bands
15 pF capacitor with Self-Resonant Frequency in 1800/1900 MHz range (e.g. Murata
GRM1555C1E150J) to filter transmission EMI in the DCS/PCS bands
A series ferrite bead for GHz band noise can be placed close to the VCC pins of the module for
additional noise filtering, but in general it is not strictly required:
Ferrite bead specifically designed for EMI noise suppression in GHz band (e.g. Murata
BLM18EG221SN1) implementing the circuit described in
to filter out EMI in all the GSM
bands. The ferrite bead can be replaced with a 0 (zero)
Ω
jumper.
☞
For devices integrating an internal antenna, it is recommended to provide space to allocate all the
components shown in
and listed in
. The mounting of each single component
depends on the specific application design.
