Ublox NINA-B50 Series, Руководство по интеграции оборудования

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NINA-B50 series - Hardware integration manual
UBX-22021116 - R02 Design-in Page 31 of 57
C1-Public
Table 7 describes the ESD immunity requirements as defined by CENELEC EN 61000-4-2, ETSI EN
301 489-1, ETSI EN 301 489-7, ETSI EN 301 489-24.
Parameter Min. Typical Max. Unit Remarks
ESD immunity. All exposed surfaces of the
radio equipment and ancillary equipment in a
representative configuration 8* kV Indirect discharge according to IEC 61000-4-2
ESD sensitivity, tested for all pins except ANT
and RSVD pins #11, #15, #33 2.0* kV Human body model according to JEDEC JS001
* Test pending
Table 7 : Electro-Magnetic Compatibility ESD immunity requirements
NINA-B50 is manufactured with consideration to the specific standards for minimizing the
occurrence of ESD events. The highly automated process complies with the IEC61340-5-1 (STM5.2-
1999 Class M1 devices) standard, and designers should implement proper measures to protect
devices from ESD events on any pin that might be exposed to the end user.
Compliance with standard protection level specified in the EN61000-4-2 is achieved by including ESD
protection as close to any areas accessible to the end user.
3.7 Design-in checklists
3.7.1 Schematic checklist
 All module pins are properly numbered and designated in the schematic (including thermal pins).

Power supply design complies with the specification.
 The power sequence is properly implemented.
 Adequate bypassing is included in front of each power pin.
 Each signal group is consistent with its own power rail supply or proper signal translation has been
provided.

Configuration pins are properly set at bootstrap.
 SDIO bus includes series resistors and pull-ups, if needed.

Unused pins are properly terminated.
 A pi-filter is provided in front of each antenna for final matching.

Additional RF co-location filters have been considered in the design.
3.7.2 Layout checklist
 PCB stack-up and controlled impedance traces follow the recommendations given by the PCB
manufacturer.
 All pins are properly connected, and the footprint follows u-blox pin design recommendations.

Proper clearance is provided between the RF and digital sections of the design.
 Proper isolation is provided between antennas (RF co-location, diversity, or multi-antenna design).

Bypass capacitors have been placed close to the module.
 Controlled impedance traces are properly implemented in the layout (both RF and digital) and the
recommendations provided by the PCB manufacturer have been followed.
 50
Ω
RF traces and connectors follow the rules described in Antenna Integration .
 Antenna design is reviewed by the antenna manufacturer.

Proper grounding is provided to the module for the low impedance return path and heat sink.
 Reference plane skipping is minimized for high frequency busses.
 All traces and planes are routed inside the area defined by the main ground plane.
 u-blox has reviewed and approved the PCB 3 .
3 Applicable only for end-products based on u-blox reference designs