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TOBY-L2 and MPCI-L2 series - System Integration Manual
UBX-13004618 - R07
Advance Information
System description
Page 51 of 158
AT+UPSV=2: power saving enabled and controlled by the RTS line
This configuration can only be enabled with the module hardware flow control disabled (i.e. AT&K0 setting).
The UART interface is immediately disabled after the DTE sets the
RTS
line to OFF.
Afterwards, the UART is enabled again, and the module does not enter low power idle-mode, as following:
If an OFF-to-ON transition occurs on the
RTS
input line, this causes the UART / module wake-up after ~5 ms:
recognition of subsequent characters is guaranteed only after the complete wake-up, and the UART is kept
enabled as long as the
RTS
input line is set to ON.
If the module needs to transmit some data over the UART (e.g. URC)
If a data call with external context is activated
If the DTE sends data, the first character sent causes the UART and module wake-up after ~5 ms: the
recognition of subsequent characters is guaranteed only after the complete wake-up, and the UART will be
then kept enabled after the last data received according to the timeout previously set with the AT+UPSV=1
configuration (see the following subsection “wake up via data reception”)
The module automatically enters the low power idle-mode whenever possible but it wakes up to active-mode
according to any required activity related to the network (e.g. for the periodic paging reception described in
section 1.5.1.5, or for any other required RF transmission / reception) or any other required activity related to the
module functions / interfaces (including the UART itself).
The hardware flow-control output (
CTS
line) indicates when the UART interface is enabled (data can be sent and
received) as illustrated in Figure 22, even if hardware flow control is disabled with AT+UPSV=2 configuration.
AT+UPSV=3: power saving enabled and controlled by the DTR line
The UART interface is immediately disabled after the DTE sets the
DTR
line to OFF.
Afterwards, the UART is enabled again, and the module does not enter low power idle-mode, as following:
If an OFF-to-ON transition occurs on the
DTR
input line, this causes the UART / module wake-up after ~5
ms: recognition of subsequent characters is guaranteed only after the complete wake-up, and the UART is
kept enabled as long as the
DTR
input line is set to ON
If the module needs to transmit some data over the UART (e.g. URC)
If a data call with external context is activated
If the DTE sends data, the first character sent causes the UART and module wake-up after ~5 ms:
recognition of subsequent characters is guaranteed only after the complete wake-up, and the UART will be
then kept enabled after the last data received according to the timeout previously set with the AT+UPSV=1
configuration (see the following subsection “wake up via data reception”)
The module automatically enters the low power idle-mode whenever possible but it wakes up to active-mode
according to any required activity related to the network (e.g. for the periodic paging reception described in
section 1.5.1.5, or for any other required RF signal transmission or reception) or any other required activity
related to the functions / interfaces of the module.
The AT+UPSV=3 configuration can be enabled regardless the flow control setting on UART. In particular, the HW
flow control can be enabled (AT&K3) or disabled (AT&K0) on UART during this configuration. In both cases, the
CTS
line indicates the UART power saving state as illustrated in Figure 22.
When the AT+UPSV=3 configuration is enabled, the
DTR
input line can still be used by the DTE to control the
module behavior according to AT&D command configuration (see
u-blox AT commands Manual