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TOBY-L2 and MPCI-L2 series - System Integration Manual
UBX-13004618 - R07
Advance Information
Design-in
Page 116 of 158
R2
LDO regulator
ELLA-W1 series
Wi-Fi module
3V3
VCC
U1
C1
R1
Wi-Fi enable
SD_D0
15
SD_D1
16
SD_D2
11
SD_D3
12
SD_CLK
14
SD_CMD
13
PDn
9
OUT
IN
SENSE
BYP
SHDNn
GND
TOBY-L2xx-50S
cellular module
SDIO_D0
66
SDIO_D1
68
SDIO_D2
63
SDIO_D3
67
SDIO_CLK
64
SDIO_CMD
65
V_INT
5
GPIO1
21
C3
3V3
4
C5
LDO regulator
1V8
VCC
U2
C2
OUT
IN
SENSE
BYP
SHDNn
GND
C4
VIO
5
C6
1V8
6
R3
R4
R5
R6
R7
RESETn
10
SLEEP_CLK
19
CFG
20
LED_0
2
R9
GND
ANT1
29
ANT2
26
R8
DL1
GND
Band-Pass filter
L1
Wi-Fi
antenna
FL1
Figure 65: Application circuit for connecting TOBY-L2xx-50S cellular modules to u-blox ELLA-W1 series Wi-Fi modules
Reference
Description
Part Number - Manufacturer
C1, C2
1 µF Capacitor Ceramic X7R 0603 10% 25 V
GRM188R71E105KA12 - Murata
C3, C4
10 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R71C103KA01 - Murata
C5, C6
10 µF Capacitor Ceramic X5R 0603 20% 6.3 V
GRM188R60J106ME47 - Murata
DL1
LED Green SMT 0603
LTST-C190KGKT - Lite-on Technology Corporation
FL1
WLAN band-pass filter with LTE Band 7 coexistence
B39242B9604P810 - TDK EPCOS
L1
15 nH Multilayer Inductor 0603 3% 0.25 A
MLG0603P15NHT000 - TDK
R1
470 k
Resistor 0402 5% 0.1 W
RK73B1ETTD474J - KOA
R2, R3, R4, R5, R6, R7 22
Resistor 0402 5% 0.1 W
RK73B1ETTP220J - KOA
R8
470
Resistor 0402 5% 0.1 W
RK73B1ETTP471J - KOA
R9
47 k
Resistor 0402 5% 0.1 W
RK73B1ETTD473J - KOA
U1
LDO Linear Regulator 3.0 V 0.3 A
LT1962EMS8-3.3 - Linear Technology
U2
LDO Linear Regulator 1.8 V 0.3 A
LT1962EMS8-1.8 - Linear Technology
Table 40: Components for connecting TOBY-L2xx-50S cellular modules to u-blox ELLA-W1 series Wi-Fi modules
Do not apply voltage to any SDIO interface pin before the switch-on of SDIO interface supply source
(
V_INT
), to avoid latch-up of circuits and allow a proper boot of the module.
ESD sensitivity rating of SDIO interface pins is 1 kV (HMB according to JESD22-A114). Higher protection
level could be required if the lines are externally accessible and it can be achieved by mounting a very low
capacitance ESD protection (e.g. Tyco Electronics PESD0402-140 ESD), close to accessible points.
If the SDIO interface pins are not used, they can be left unconnected on the application board.
2.6.4.2
Guidelines for SDIO layout design
The SDIO
serial interface requires the same consideration regarding electro-magnetic interference as any other
high speed digital interface.
Keep the traces short, avoid stubs and avoid coupling with RF lines / parts or sensitive analog inputs, since the
signals can cause the radiation of some harmonics of the digital data frequency.
Consider the usage of low value series damping resistors (see the application circuit in Figure 65 / Table 40) to
avoid reflections and other losses in signal integrity, which may create ringing and loss of a square wave shape.