LISA-U2 series - System Integration Manual
UBX-13001118 - R19
Early Production Information
System description
Page 61 of 175
1.9.2.3
UART and power-saving
The power saving configuration is controlled by the AT+UPSV command (for the complete description see the
u-blox AT Commands Manual
[2]). When power saving is enabled, the module automatically enters low power
idle-mode whenever possible; otherwise the active-mode is maintained by the module (see section 1.4 for the
definition and description of module operating modes).
The AT+UPSV command configures both the module power saving and also the UART behavior in relation to the
power saving. The conditions for the module entering idle-mode also depend on the UART power saving
configuration.
The AT+UPSV command can set these different power saving configurations:
AT+UPSV=0, power saving disabled: module forced on active-mode and UART interface enabled (default)
AT+UPSV=1, power saving enabled: module cyclic active / idle-mode and UART enabled / disabled
AT+UPSV=2, power saving enabled and controlled by the UART
RTS
input line
AT+UPSV=3, power saving enabled and controlled by the UART
DTR
input line
The AT+UPSV=3 power saving configuration is not supported by “01” product version
The different power saving configurations that can be set by the +UPSV AT command are described in details in
the following subsections. UART interface communication process in the different power saving configurations,
in relation with HW flow control settings and
RTS
input line status, is summarized in Table 28. For more details
on the +UPSV AT command description, see the
u-blox AT commands Manual
AT+UPSV HW flow control
RTS line
DTR line
Communication during idle-mode and wake up
0
Enabled (AT&K3)
ON
ON or OFF
Data sent by the DTE is correctly received by the module.
Data sent by the module is correctly received by the DTE.
0
Enabled (AT&K3)
OFF
ON or OFF
Data sent by the DTE should be buffered by the DTE and will be correctly
received by the module when RTS is set to ON.
Data sent by the module is buffered by the module and will be correctly
received by the DTE when it is ready to receive data (i.e.
RTS
line will be ON).
0
Disabled (AT&K0)
ON or OFF
ON or OFF
Data sent by the DTE is correctly received by the module.
Data sent by the module is correctly received by the DTE if it is ready to receive
data, otherwise the data is lost.
1
Enabled (AT&K3)
ON
ON or OFF
Data sent by the DTE should be buffered by the DTE and will be correctly
received by the module when active-mode is entered.
Data sent by the module is correctly received by the DTE.
1
Enabled (AT&K3)
OFF
ON or OFF
Data sent by the DTE is buffered by the DTE and will be correctly received by
the module when active-mode is entered.
Data sent by the module is buffered by the module and will be correctly
received by the DTE when it is ready to receive data (i.e.
RTS
line will be ON).
1
Disabled (AT&K0)
ON or OFF
ON or OFF
The first character sent by the DTE is lost, but after ~20 ms the UART and the
module are waked up: recognition of subsequent characters is guaranteed
after the complete UART / module wake-up.
Data sent by the module is correctly received by the DTE if it is ready to receive
data, otherwise data is lost.
