LISA-U2 series - System Integration Manual
UBX-13001118 - R19
Early Production Information
System description
Page 104 of 175
1.14
Schematic for LISA-U2 module integration
Figure 54 is an example of a schematic diagram where LISA-U2 series module is integrated into an application
board, using all the interfaces of the module.
TXD
RXD
RTS
CTS
DTR
DSR
RI
DCD
GND
15
TXD
12
DTR
16
RXD
13
RTS
14
CTS
9
DSR
10
RI
11
DCD
GND
3V8
GND
LISA-U2 series
62
VCC
63
VCC
61
VCC
+
100µF
2
V_BCKP
MOSI
MISO
SCLK
Interrupt
GPIO
GND
56
SPI_MOSI
59
SPI_MRDY
57
SPI_MISO
55
SPI_SCLK
58
SPI_SRDY
GND
VBUS
D+
D-
GND
18
VUSB_DET
27
USB_D+
26
USB_D-
GND
100nF
5
RSVD
74
ANT_DIV
GND
RTC
back-up
u-blox GNSS
1.8V Receiver
4.7k
OUT
IN
GND
LDO Regulator
SHDN
SDA
SCL
4.7k
3V8
1V8_GPS
SDA2
SCL2
GPIO3
GPIO4
TxD1
EXTINT0
46
45
23
24
47k
VCC
GPIO2
21
ANT
68
Main Tx/Rx
Antenna
1.8V DTE
1.8V SPI Master
USB 2.0 Host
20
GPIO1
3V8
Network
Indicator
22
RESET_N
Ferrite
Bead
47pF
Application
Processor
Open
Drain
Output
19
PWR_ON
100k
Ω
Open
Drain
Output
0
Ω
0
Ω
TP
TP
0
Ω
0
Ω
TP
TP
1.8V Digital
Audio Device
I2S_RXD
I2S_CLK
I2S Data Output
I2S Clock
I2S_TXD
I2S_WA
I2S Data Input
I2S Word Alligment
44
43
42
41
Rx Diversity
Antenna
LISA-U230 only
47pF
SIM Card Holder
CCVCC (C1)
CCVPP (C6)
CCIO (C7)
CCCLK (C3)
CCRST (C2)
GND (C5)
47pF 47pF
100nF
50
VSIM
48
SIM_IO
47
SIM_CLK
49
SIM_RST
47pF
SW1
SW2
4
V_INT
51
GPIO5
470k
1k
ESD ESD ESD ESD ESD ESD
V_INT
220nF
V_INT
BCLK
LRCLK
10µF
1µF
Audio Codec
MAX9860
SDIN
SDOUT
SDA
SCL
53
I2S1_CLK
54
I2S1_WA
40
I2S1_TXD
39
I2S1_RXD
52
CODEC_CLK
MCLK
IRQn
10k
100nF
VDD
SPK
OUTP
OUTN
MIC
MICBIAS
1µF
2.2k
1µF
1µF
MICLN
MICLP
MICGND
2.2k
ESD ESD
27pF
27pF
V_INT
EMI
EMI
10nF
10nF
EMI
EMI
ESD ESD
27pF
27pF
10nF
10nF
330µF
10nF
100nF
15pF 68pF
Ferrite
Bead
Figure 54: Example of schematic diagram to integrate LISA-U2 series modules in an application board, using all the interfaces