LISA-U2 series - System Integration Manual
UBX-13001118 - R19
Early Production Information
System description
Page 80 of 175
1.9.4.3
IPC communication examples
In the following, three IPC communication scenarios are described:
Slave initiated data transfer, with a sleeping master
Master initiated data transfer, with a sleeping slave
Slave ended data transfer
Slave initiated transfer with a sleeping master
Figure 42: Data transfer initiated by LISA-U2 module (slave), with a sleeping application processor (master)
When the master is sleeping (idle-mode), the following actions happen:
1.
The slave indicates the master that is ready to send data by activating
SPI_SRDY
2.
When the master becomes ready to send, it signalizes this by activating
SPI_MRDY
3.
The master activates the clock and the two processors exchange the communication header and data
4.
If the data has been exchanged, the slave deactivates
SPI_SRDY
to process the received information. The
master does not need to de-assert
SPI_MRDY
as it controls the
SPI_SCLK
5.
After the preparation, the slave activates again
SPI_SRDY
and wait for
SPI_SCLK
activation. When the clock
is active, all the data is transferred without intervention. If there is more data to transfer (flag set in any of
the headers), the process will repeat from step 3
Master initiated transfer with a sleeping slave
Figure 43: Data transfer initiated by application processor (master) with a sleeping LISA-U2 module (slave)
When the slave is sleeping (idle-mode), the following actions happen:
1.
The Master wakes the slave by setting the
SPI_MRDY
line active
2.
As soon as the slave is awake, it signals it by activating
SPI_SRDY
3.
The master activates the clock and the two processors exchange the communication header and data
SPI_MRDY
SPI_SRDY
DATA EXCHG
1
2
4
5
Header
Data
Header
3
SPI_MRDY
SPI_SRDY
DATA EXCHG
2
4
5
Header
Data
Header
3
1