LISA-U2 series - System Integration Manual
UBX-13001118 - R19
Early Production Information
Design-In
Page 124 of 175
2.2.2
Footprint and paste mask
The following figure describes the footprint and provides recommendations for the paste mask for LISA-U2
modules. These are recommendations only and not specifications. Note that the copper and solder masks have
the same size and position.
33
.2
m
m
[
13
07
.1
m
il]
22.4 mm [881.9 mil]
2.
3
m
m
[90.
6
m
il]
0.
8
m
m
[31.
5
m
il]
1.
1
m
m
[43.
3
m
il]
0.
8
m
m
[31.
5
m
il]
1.0 mm
[39.3 mil]
5.7 mm
[224.4 mil]
33
.2
m
m
[
13
07
.1
m
il]
22.4 mm [881.9 mil]
2.
3
m
m
[90
.6
m
il]
1.
2
m
m
[47
.2
m
il]
1.
1
m
m
[43
.3
m
il]
0.
8
m
m
[31
.5
m
il]
0.9 mm
[35.4 mil]
5.7 mm
[224.4 mil]
0.
6
m
m
[23
.6
m
il]
Stencil: 150 µm
Figure 61: LISA-U2 modules suggested footprint and paste mask
To improve the wetting of the half vias, reduce the amount of solder paste under the module and increase the
volume outside of the module by defining the dimensions of the paste mask to form a T-shape (or equivalent)
extending beyond the copper mask. The solder paste should have a total thickness of 150 µm.
The paste mask outline needs to be considered when defining the minimal distance to the next
component.
The exact geometry, distances, stencil thicknesses and solder paste volumes must be adapted to the
specific production processes (e.g. soldering etc.) of the customer.
The implemetation of a step stencil (a stencil with different material thicknesses) should be considered if very
different sized components must be soldered on the same application PCB: while high density chip housings
with small pitch need small solder paste quantities for the avoidance of short-circuits and therefore require thin
stencils, large components need more solder paste for a safe connection and thus thicker stencils.
The bottom layer of LISA-U2 series modules has two unprotected copper areas for GND, shown in Figure 62.
Consider “No-routing” areas for the LISA-U2 modules footprint as follows: signal keep-out area on the
top layer of the application board, below LISA-U2 modules, due to GND opening on module bottom layer
(see Figure 62).
