u-blox SARA-G3 Series, Руководство по системной интеграции

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SARA-G3 series - System Integration Manual
UBX-13000995 - R06 Objective Specification Design-in
Page 113 of 218
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Select an integrated antenna solution provided by an antenna manufacturer if the required
ground plane dimensions are large enough according to the related integrated antenna solution
specifications: the antenna selection and the definition of its placement in the product layout
should begin at the start of the product design process
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It is highly recommended to strictly follow the detailed and specific guidelines provided by the
antenna manufacturer regarding correct installation and deployment of the antenna system,
including PCB layout and matching circuitry
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Further to the custom PCB and product restrictions, the antenna may require a tuning to
comply with all the applicable required certification schemes. It is recommended to ask the
antenna manufacturer for the design-in guidelines for the antenna related to the custom
application
In both cases, selecting an external or an internal antenna, observe these recommendations:
 Select an antenna providing optimal return loss (or V.S.W.R.) figure over all the operating
frequencies

Select an antenna providing optimal efficiency figure over all the operating frequencies

Select an antenna providing appropriate gain figure (i.e. combined antenna directivity and efficiency
figure) so that the electromagnetic field radiation intensity do not exceed the regulatory limits specified
in some countries (e.g. by FCC in the United States, as reported in section 4.2.2)
For the additional specific guidelines for SARA-G350 ATEX modules integration in potentially
explosive atmospheres applications, refer to section 2.13.
2.3.1.2 Guidelines for antenna RF interface design
Guidelines for ANT pin RF connection design
Proper transition between the ANT pad and the application board PCB must be provided, implementing the
following design-in guidelines for the layout of the application PCB close to the ANT pad:
 On a multi layer board, the whole layer stack below the RF connection should be free of digital lines
 Increase GND keep-out (i.e. clearance, a void area) around the ANT pad, on the top layer of the
application PCB, to at least 250 µm up to adjacent pads metal definition and up to 400 µm on the
area below the module, to reduce parasitic capacitance to ground, as described in the left picture in
Figure 37Figure 37
 Add GND keep-out (i.e. clearance, a void area) on the buried metal layer below the ANT pad if
the top-layer to buried layer dielectric thickness is below 200 µm, to reduce parasitic capacitance to
ground, as described in the right picture in
Figure 37Figure 37