JODY-W2 - System integration manual
UBX-18068879 - R14
System description
Page 17 of 84
C1 - Public
High Speed UART interface
The JODY-W2 series modules support a high-speed Universal Asynchronous Receiver/Transmitter
(UART) interface in compliance with the industry standard 16550 specification. The main features of
the UART interface are:
•
FIFO mode permanently selected for transmit and receive operations
•
Two pins for transmit and receive operations
•
Two flow control pins (RTS/CTS)
•
Interrupt triggers for low-power, high throughput operation
•
Supports standard baud rates and high throughput up to 4 Mbit/s. The default baud rate after
reset is 3000000 baud.
The UART interface operation includes:
•
Uploading the firmware to the module
•
Bluetooth data
Name
I/O
Description
Remarks
BT_UART_TX
O
UART TX signal
Connect to Host RX. Used as configuration pin. See also
BT_UART_RX
I
UART RX signal
Connect to Host TX
BT_UART_RTS
O
UART RTS signal
Connect to Host CTS. Used as configuration pin. See also
BT_UART_CTS
I
UART CTS signal
Connect to Host RTS
Table 11: UART signal description
High Speed UART signals are powered by the
VIO
voltage domain.
PCM - Audio interface
JODY-W2 series modules provide one bi-directional 4-wire PCM digital audio interface that can be
used for digital audio communication with external digital audio devices as an audio codec. The PCM
interface supports:
•
Master or slave mode
•
PCM bit width size of 8 bit or 16 bit
•
Up to 4 slots with configurable bit width and start positions
•
Short frame and long frame synchronization
Name
I/O
Description
Remarks
PCM_CLK
I/O
PCM clock
Output if Master, Input if Slave
PCM_SYNC
I/O
PCM frame sync
Output if Master, Input if Slave
PCM_IN
I
PCM data in
PCM_OUT
O
PCM data out
Used as configuration pin. See also
Table 12: PCM digital audio signal description
The PCM signals are powered by the VIO voltage domain.
Low power oscillator
For professional grade modules, an optional external low-frequency clock for low-power mode timing
can be connected to the
LPO_IN
pin. The external LPO must meet the requirements listed in
If no external sleep clock is used, leave this pin unconnected.