u-blox JODY-W2, Руководство по системной интеграции

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JODY-W2 - System integration manual
UBX-18068879 - R14 System description Page 12 of 84
C1 - Public
Table 4: JODY-W2 pin description
Main supply inputs
JODY-W2 series modules are supplied through the VBAT/VIO/1V8 pins. VBAT supplies power to the
internal power management circuitry that includes a SMPS converter and a LDO that source the
system ASIC.
The current drawn by the JODY-W2 series through the
VBAT pin can vary by several orders of
magnitude depending on the operation mode and state. It changes from high current consumption
during Wi-Fi transmission at maximum RF power level in connected-mode to low current consumption
during low power idle-mode with the power saving configuration enabled.
The electrical requirements for supply voltages are described in the JODY-W2 series data sheet
[2] .
No. Name Chip pin I/O
1
Description Domain
42 GPIO_0 GPIO[0] I/O VIO
43-48 NC NC Reserved (Do not connect) -
49 GND GND Ground GND
50 SD_D2 SD_DAT[2] I/O SDIO data line bit [2] 1V8
51 SD_D3 SD_DAT[3] I/O SDIO data line bit [3] 1V8
52 SD_CMD SD_CMD I/O SDIO Command line 1V8
53 SD_CLK SD_CLK I SDIO Clock input 1V8
54 SD_D0 SD_DAT[0] I/O SDIO data line bit [0] 1V8
55 SD_D1 SD_DAT[1] I/O SDIO data line bit [1] 1V8
56 NC NC Reserved (Do not connect) -
57 PG OD Open-drain output from the internal DC/DC converter,
which indicates the power quality of the 2.2 V rail. High
impedance indicates power good. Low level indicates
2.2 V is not in power good.
A (100 k
Ω
) pull-up resistor must be connected to this pin
to detect the power good state.
-
58 PDn PDn I Power-down interface of the chipset:
0 = power-down mode
1 = normal mode
Can accept an input of 1.8 V to 4.5 V.
No Internal pull-up on this pin. 1V8
59 CORE_PDn I Enable pin of the core voltage regulator:
0 = power supply off
Connect with PDn 1V8
60 LPO_IN SPL_CLK_IN I Sleep clock input (optional)
32.768 kHz clock input used for lower power operation in
sleep mode.
Only supported on professional grade variants:JODY-
W263-xxB VIO
- Exposed Pins GND 15 Ground/Thermal exposed pins
Connect to ground, see also
Thermal guidelines
GND