4. Register Descriptions
122
Tsi308 User Manual
80D4000_MA001_02
Tundra Semiconductor Corporation
www.tundra.com
4.3.5.37
HyperTransport Link 0 Control Register
Register Offset : 45h–44h
Bit
R/W
Access
Initial
Value
Field Name and Description
15
R(SP/DSP)
R/W(GSP/
GDP)
0h
SP/DSP:
Reserved
GSP/GDP:
64 Bit Addressing Enable
If set Tsi308 accepts requests from HT that access addresses above
FF_FFFF_FFFFh when issued with Address Extension command. If this bit is
clear, then any request from HT that access above FF_FFFF_FFFFh will be
master aborted by Tsi308 as if end of chain was reached.
Similarly when this bit is clear, any request from PCI/PCI-X that access above
FF_FFFF_FFFFh will be master aborted on PCI/PCI-X. If this bit is set then for
requests from PCI/PCI-X that access above FF-FFFF-FFFFh, Tsi308 uses
Address Extension command to forward them onto HT.
Not persistent through warm reset.
14
R/C(SP/DS
P)
R/W (GSP/
GDP)
0
SP/DSP:
NXA Error:
This bit is set whenever a response or posted write is dropped due to hitting end of
chain. It can be cleared by writing a 1 to it. Persistent through warm reset.
GSP/ GDP:
Extended CTL Time:
If this bit is set during the link initialization following LDTSTOP# disconnect
sequence, CTL will be asserted for 50us
13
R/C(SP/DS
P)
R/W (GSP/
GDP)
0
SP/DSP:
Overflow Error:
This bit is set whenever an overflow error is detected. It may be cleared by writing
a 1 to it. Persistent through warm reset.
GSP/ GDP:
LDTSTOP# Tristate Enable:
This bit controls whether the transmitter tristates the link during LDTSTOP#
sequence. When this bit is set, transmitter tristates the link. When this bit is clear,
transmitter continues to drive the link.
Содержание TSI308
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