User's Manual l MBa8MPxL UM 0100 l © 2022, TQ-Systems GmbH
Page 27
Pin header (continued)
Table 22:
Pinout header X61
Dir.
Level
Group
Signal
Pin Pin
Signal
Group
Level
Dir.
O
5 V
Power
V_5V_SW
1
2
V_1V8
Power
1.8 V
O
I
1.8 V
CCM
CLK1_IN
3
4
V_3V3_MB
Power
3.3 V
O
I
1.8 V
CCM
CLK2_IN
5
6
GND
Power
Ground
–
–
Ground
Power
GND
7
8
I2C6_SDA
SD
V_SD1
I/O
9
10
I2C6_SCL
SD
V_SD1
O
I
V_SD1
SD
UART1_RX
11
12
GND
Power
Ground
–
O
V_SD1
SD
UART1_TX
13
14
PMIC_WDOG_IN#
TQMa8MPxL
3.3 V
I
–
Ground
Power
GND
15
16
GND
Power
Ground
–
I
V_SD1
SD
UART2_RX
17
18
QSPI1A_SCLK
NAND
1.8 V
O
O
V_SD1
SD
UART2_TX
19
20
QSPI1A_DATA0
NAND
1.8 V
I/O
–
Ground
Power
GND
21
22
QSPI1A_DATA1
NAND
1.8 V
I/O
–
–
–
NC
23
24
QSPI1A_DATA2
NAND
1.8 V
I/O
25
26
QSPI1A_DATA3
1
NAND
1.8 V
I/O
27
28
QSPI1A_SS0#1
NAND
1.8 V
O
29
30
GND
Power
Ground
–
31
32
ISO_7816_CLK
TQMa8MPxL
3.3 V
I
–
Ground
Power
GND
33
34
ISO_7816_RST
TQMa8MPxL
3.3 V
I
I/O V_SAI2_SAI3
GPIO
SPDIF_EXT_CLK
35
36
ISO_7816_IO1
TQMa8MPxL
3.3 V
I/O
I
V_SAI2_SAI3
GPIO
SPDIF_IN
37
38
ISO_7816_IO2
TQMa8MPxL
3.3 V
I/O
O
V_SAI2_SAI3
GPIO
SPDIF_OUT
39
40
GND
Power
Ground
–
Table 23:
Pinout header X63
Dir.
Level
Group
Signal
Pin
Pin
Signal
Group
Level
Dir.
O
5 V
Power
V_5V_SW
1
2
V_1V8
Power
1.8 V
O
–
Ground
Power
GND
3
4
V_3V3_MB
Power
3.3 V
O
I
1.8 V
ENET
ENET0_EVENT1_IN
5
6
GND
Power
Ground
–
O
1.8 V
ENET0_EVENT1_OUT
7
8
ECSPI2_CS0
ECSPI_HDMI
1.8 V
O
–
Ground
Power
GND
9
10
ECSPI2_MISO
ECSPI_HDMI
1.8 V
I/O
I
1.8 V
ENET
ENET1_EVENT2_IN
11
12
ECSPI2_MOSI
ECSPI_HDMI
1.8 V
O
O
1.8 V
ENET1_EVENT2_OUT
13
14
ECSPI2_SCLK
ECSPI_HDMI
1.8 V
O
–
Ground
Power
GND
15
16
GND
Power
Ground
–
17
18
GPT1_CLK
I2C_UART
3.3 V
I/O
I
3.3 V
GPIO
M7_NMI
19
20
GPT1_CPTR2
I2C_UART
3.3 V
I
1
If 0 Ω bridges are placed, otherwise NC