User's Manual l MBa8MPxL UM 0100 l © 2022, TQ-Systems GmbH
Page 18
3.3.7
MIPI DSI / DisplayPort
The TQMa8MPxL MIPI DSI interface, consisting of a differential clock signal and four differential data lines,
is routed on the MBa8MPxL to DisplayPort connector X65 via a Toshiba TC9595XBG DSI-to-DisplayPort bridge.
The bridge supports DisplayPort 1.1a standard and thus resolutions of 1920x1200 at 60 FPS.
3.3 V is available at the DisplayPort connector, which can supply a maximum of 500 mA.
This current must be subtracted from
the current budget of the LM25119.
The TC9595's reference clock is generated by a 26 MHz oscillator, which is connected to the REFCLK input.
TC9595XBG
TQMa8MPxL
MIPI_DSI
I2C1_1V8
DisplayPort
DSI
I2C
DP[1:0]
AUX
HPD
V_3V3_MB
(max. 500 mA)
ESD
Figure 15: Block diagram DisplayPort
Table 12:
Pinout DisplayPort, X65
Pin
Signal
Remark
1
–
2
DGND
–
3
DP_ML0–
–
4
–
5
DGND
–
6
DP_ML1–
–
7
(NC)
–
8
DGND
–
9
(NC)
–
10
(NC)
–
11
DGND
–
12
(NC)
–
13
DP_CFG1
1 MΩ termination
14
DP_CFG2
1 MΩ termination
15
DP
100 kΩ PD
16
DGND
–
17
DP_AUX_CH–
100 kΩ PU to 3.3 V
18
DP_HPD
100 kΩ PD; GPIO0 at DP bridge
19
DGND
–
20
V_3V3_DP
Max. 500 mA
M1…4
Shield / DGND
–
