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TOSHIBA G9000 UPS White Paper
© 2008 TOSHIBA INTERNATIONAL CORPORATION – INDUSTRIAL DIVISION Page 4
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UPSG9000WP081201
An alternative power conversion circuit arrangement called multilevel
3
features several advantages over the conventional two-level converter
including:
n
lower voltage stresses on power semiconductors devices;
n
considerable reduction of acoustic noise and electromagnetic
interference;
n
higher efficiency (lower losses);
n
higher reliability;
n
compactness.
The most common multilevel structure is shown in Figure 5. In this
sophisticated arrangement note that:
n
the voltage stress on each power switch is equal to E/2 Volts.
n
the output voltage at each terminal assumes one out of three levels:
+E/2, 0 and –E/2 Volts.
This observation shows that:
n
voltage stresses on power switches are half of those in the
conventional circuit;
n
the voltage variation ( dv/dt ) at each terminal is equal to E/2 Volts.
These findings imply that
n
voltage ratings of power semiconductors can be half of those in the
conventional circuit widening design options.
n
significant noise reduction (acoustic noise and electromagnetic
interference) is associated with the lower dv/dt .
Due to this additional voltage level, the number of combinations to
3
The term multilevel was firstly coined in the paper: A. Nabae, I. Takahashi, and H. Akagi, “A new neutral-point-clamped PWM
inverter”, IEEE Trans. Ind. Applicat. Vol. IA-17, No. 5 (1981).
FIGURE 5
A multilevel (3-level)
3-phase inverter
circuit