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Model P5000HX Series CPU User’s Manual
Component Descriptions (cont.)
Overview
Additional components are described below.
PCI Interface
The PIIX3 incorporates a fully PCI Bus compatible master
and slave interface. As a PCI master, the PIIX3 runs cycles
on behalf of DMA, ISA masters, or a bus master IDE. As a
PCI slave, the PIIX3 accepts cycles initiated by PCI mas-
ters targeted for the PIIX3’s internal register set of the
ISA bus. The PIIX3 directly supports the PCI interface
running at either 25 MHz, 30 MHZ, or 33 MHz. Also, the
PIIX3 supports the standard PCI cycle terminations as
described in the PCI local configuration.
Timer Block
The timer block contains three counters that are equiva-
lent in function to those found in one 82C54 programma-
ble interval timer. These three counters are combined to
provide the System Timer function, Refresh Request, and
speaker tone.
Utility Bus (X-Bus)
Logic
Chip selects for Flash BIOS, real time clock, keyboard/
mouse controller, floppy controller, two serial ports, one
parallel port, and an IDE hard disk drive. The PIIX3 pro-
vides the control for the buffer that isolates the lower 8
bits of the ISA bus.
Interrupt Controller
Block
The PIIX3 provides an ISA-compatible interrupt controller
that incorporates the functionality of two 82C59 interrupt
controllers.
