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Model P5000HX Series CPU User’s Manual
4.3
Component Descriptions
Overview
This section provides information on P5000HX
components.
CPU
The Enhanced P5000HX PCI/ISA is designed to operate
with a 100/133/166/200 MHz Pentium microprocessor. It
supports both read and write burst mode bus cycles and
includes an on-chip 16 KB cache that is split into 8 KB
code and data caches employing a write-back policy.
The Pentium processor also integrates an advanced
numeric coprocessor that significantly increases the speed
of floating point operations, while maintaining compatibil-
ity with i486DX math coprocessor and compliance with
ANSI/IEEE standard 754-1985.
Second Level Cache
The Pentium processor’s internal cache is complemented
with a 256/512 KB write-back second-level cache imple-
mented with optional pipelined burst SRAM modules. Tag
and control logic is contained in the 82430HX TXC core
chip. External tag 16k x 4 has been added for cacheability
detection of up to 512KB cache.
Triton II Xcellerated
Controller (TXC)
The Triton II Xcellerated Controller (TXC) is a single chip
host-to -PCI bridge providing second level cache control
and DRAM control functions. The second level cache (L2)
supports a write-back cache policy for cache sizes of 256K
and 512KB. The TXC provides a 64/72 bit data path to
main memory, and memory sizes of 4M up to 512Mb are
supported. The DRAM controller provides eight Rows and
optional DRAM error detection/correction (EDC) or parity.
The TXC’s optimized PCI interface allows the CPU to sus-
tain the highest possible bandwidth to the graphics frame
buffer at all supported frequencies.
