Hardware Configuration
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3.2
Switches, Jumpers, and LEDs
3.2.1
Switches and Pushbuttons
The TSW14J50 contains several switches and pushbuttons that enable certain functions on the board.
The description of the switches is found in
Table 1
.
Table 1. Switch Description of the TSW14J50 Device
Component
Description
SW1
Spare dip switches that are connected to spare FPGA inputs
SW2 and SW3
Spare pushbutton that are connected to spare FPGA inputs
SW4 (CPU RESET)
FPGA hardware reset
SW5
Sets IO voltage of FPGA bank 5. All switches open, IO voltage = 1.4 V . Default
is switch 2 closed only to provide 1.8 V to IO of Bank 5.
SW5 switch 1 closed adds 0.2 V to 1.4 V IO voltage
SW5 switch 2 closed adds 0.4 V to 1.4 V IO voltage
SW5 switch 3 closed adds 0.8 V to 1.4 V IO voltage
SW5 switch 4 closed adds 1.6 V to 1.4 V IO voltage
3.2.2
Jumpers
The TSW14J50 contains several jumpers (JP) and solder jumpers (SJP) that enable certain functions on
the board. The description of the jumpers is found in
Table 2
.
Table 2. Jumper Description of the TSW14J50 Device
Component
Description
Default
JP4, JP5, JP6, and JP7
USB or JTAG control of FPGA programming. Default is USB control.
1 to 2
JP8
USB or internal 5-V power for USB interface. Default is internal power.
1 to 2
JP9
USB 3.3 V regulator enable. Default is enabled.
2 to 3
SJP2
Direction control for PIO_9 signal of buffer U29. Default is B to A.
1 to 2
SJP3
Direction control for PRESENT signal of buffer U29. Default is B to A.
2 to 3
JP10
Selects either external power or Variable power (default) net for FPGA bank 5 IO
1 to 2
supply. This is the IO voltage set by SW5.
6
TSW14J50 JESD204B High-Speed Data Capture and Pattern Generator
SLAU576 – May 2014
Card User's Guide
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