Functionality
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Figure 2
shows a block diagram of the TSW14J50 EVM.
Figure 2. TSW14J50 EVM Block Diagram
2.1
ADC EVM Data Capture
New TI high-speed ADCs and DACs now have high-speed serial data that meets the JESD204B standard.
These devices are generally available on an EVM that connects directly to the TSW14J50EVM. The
common connector between the EVMs and the TSW14J50EVM is a Samtec high-speed, high-density
FMC connector (SEAF-40-05.0-S-10-2-A-K) suitable for high-speed differential pairs up to 21 Gbps. A
common pinout for the connector across a family of EVMs has been established. At present, the interface
between the EVMs and the TSW14J50EVM has defined connections for 8 lanes of serial differential data,
two device clock pairs, two SYSREF pairs, two SYNC pairs, four over-range single-ended indicators, and
26 spare general purpose signals that can be used as CMOS I/O pins or differential LVDS signals. There
are also two differential clock input pairs.
The data format for JESD204B ADCs and DACs is a serialized format, where individual bits of the data
are presented on the serial pairs commonly referred to as lanes. Devices designed around the JESD204B
specification can have up to 8 lanes for transmitting or receiving data. The firmware in the FPGA on the
TSW14J50 is designed to accommodate any of TI's ADC or DAC operating with any number of lanes from
1 to 8.
4
TSW14J50 JESD204B High-Speed Data Capture and Pattern Generator
SLAU576 – May 2014
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