Hardware Configuration
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Table 4. FPGA FMC connector (J5) description of the TSW14J10 (continued)
DP6_M2C_P/N
B16/B17
Lane 6+/- (M->C)
JESD Serial data transmitted from Mezzanine and received by Carrier
DP7_M2C_P/N
B12/B13
Lane 7+/- (M->C)
JESD Serial data transmitted from Mezzanine and received by Carrier
DP0_C2M_P/N
C2/C3
Lane 0+/- (C->M)
JESD Serial data transmitted from Carrier and received by Mezzanine
DP1_C2M_P/N
A22/A23
Lane 1+/- (C->M)
JESD Serial data transmitted from Carrier and received by Mezzanine
DP2_C2M_P/N
A26/A27
Lane 2+/- (C->M)
JESD Serial data transmitted from Carrier and received by Mezzanine
DP3_C2M_P/N
A30/A31
Lane 3+/- (C->M)
JESD Serial data transmitted from Carrier and received by Mezzanine
DP4_C2M_P/N
A34/A35
Lane 4+/- (C->M)
JESD Serial data transmitted from Carrier and received by Mezzanine
DP5_C2M_P/N
A38/A39
Lane 5+/- (C->M)
JESD Serial data transmitted from Carrier and received by Mezzanine
DP6_C2M_P/N
B36/B37
Lane 6+/- (C->M)
JESD Serial data transmitted from Carrier and received by Mezzanine
DP7_C2M_P/N
B32/B33
Lane 7+/- (C->M)
JESD Serial data transmitted from Carrier and received by Mezzanine
GBTCLK0_M2C_P/N
D4/D5
/- (M->C)
Primary carrier-bound reference clock required for FPGA gigabit transceivers.
Equivalent to device clock.
GBTCLK1_M2C_P/M
B20/B21
Alt /- (M->C)
Alternate primary carrier-bound reference clock required for FPGA gigabit
transceivers. Equivalent to device clock.
Device Clock, SYSREF, and SYNC
FMC Signal Name
FMC Pin
Standard JESD204
Description
Application Mapping
CLK_LA0_P/N
G6/G7
/- (M->C)
Secondary carrier-bound device clock. Used for special FPGA functions such as
sampling SYSREF.
LA01_P/N_CC_A
D8/D9
/- (C->M)
Mezzanine-bound device Clock. Used for low noise conversion clock. 2.5V level
SYSREFP/N
G9/G10
/- (M->C)
Carrier-bound SYSREF signal
LA05_P/N_A
D11/D12
/- (C->M)
Mezzanine-bound SYSREF differential signal, 2.5V level
RX_SYNC_P/N
G12/G13
SYNC+/- (C>M)
ADC Mezzanine-bound SYNC signal for use in class 0/1/2 JESD204 systems
TX_SYNC_P/N
F10/F11
DAC SYNC+/- (M>C)
Carrier-bound SYNC signal for use in class 0/1/2 JESD204 systems.
TX_ALT_SYNC_P/N
F19/F20
Alt. DAC SYNC+/- (M>C)
Alternate Carrier-bound SYNC signal for use in class 0/1/2 JESD204B systems.
RX_CMOS_SYNC_P
H31
Alt. SYNC+/- (C>M)
Alternate ADC Mezzanine-bound SYNC signal. For use when SYNC (C->M) is not
available.
RX_ALT_SYNC_N
H32
Alt. SYNC+/- (C>M)
Alternate ADC Mezzanine-bound SYNC signal. For use when SYNC (C->M) is not
available.
TX_TRG
K22
TX trigger input or spare IO, adjustable level*
Special Purpose I/O
FMC Signal Name
FMC Pin
Direction
Description
PG_M2C_A
F1
FMC-to-FPGA
Power good from mezzanine to carrier
PRESENT
H2
FMC-to-FPGA
EVM Present indicator or spare IO signal, adjustable level
PIO_0
C14
FPGA-to-FMC
Spare output signal, adjustable level*
PIO_1
C15
FPGA-to-FMC
Spare output signal, adjustable level*
PIO_2
D14
FPGA-to-FMC
Spare output signal, adjustable level*
PIO_3
D15
FPGA-to-FMC
Spare output signal, adjustable level*
PIO_4
G15
FPGA-to-FMC
Spare output signal, adjustable level*
PIO_5
G16
FPGA-to-FMC
Spare output signal, adjustable level*
PIO_6
H16
FPGA-to-FMC
Spare output signal, adjustable level*
PIO_7
H17
FPGA-to-FMC
Spare output signal, adjustable level*
OVRA
K19
ADC-to-FPGA
ADC over range indicator or spare IO, adjustable level*
OVRB
E18
ADC-to-FPGA
ADC over range indicator or spare IO, adjustable level*
OVRC
J22
ADC-to-FPGA
ADC over range indicator or spare IO, adjustable level*
OVRD
J21
ADC-to-FPGA
ADC over range indicator or spare IO, adjustable level*
FPGA_CLK2P/N
J2/J3
FPGA-to-DAC
Spare IO signal, 2.5V level
FPGA_CLK1P/N
K4/K5
FPGA-to-DAC
Spare IO signal, 2.5V level
PIO_9
C18
FMC-to-FPGA
Spare IO signal, adjustable level*
LA13_P_A
D17
FPGA-to-ADC
Spare IO signal, 2.5V level
LA13_N_A
D18
FPGA-to-ADC
Spare IO signal, 2.5V level
HA20_N_A
E19
FPGA-to-FMC
Spare IO signal, adjustable level*
8
TSW14J50 JESD204B High-Speed Data Capture and Pattern Generator
SLAU576 – May 2014
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