Texas Instruments TSW1200EVM Скачать руководство пользователя страница 26

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DCLK_M

DCLK_P

FCLK_M

FCLK_P

FPGA_SDA

SH2

FPGA_SEN

SH2

FPGA_RST

SH2

FPGA_PDN

SH2

FPGA_SCLK

SH2

Input3_P

Input3_M

Input13_P

Input13_M

Input14_P

Input14_M

Input15_P

Input15_M

Input12_P

Input12_M

Input1_P

Input1_M

Input2_P

Input2_M

Input0_P

Input0_M

Input5_P

Input5_M

Input6_P

Input6_M

Input7_P

Input7_M

Input4_P

Input4_M

FCLK_P

FCLK_M

Input9_P

Input9_M

Input10_P

Input10_M

Input1

1_P

Input1

1_M

Input8_P

Input8_M

DCLK_P

DCLK_M

Input0_M

Input0_P

Input14_M

Input14_P

Input1

1_M

Input1

1_P

Input12_M

Input12_P

Input13_M

Input13_P

Input15_M

Input15_P

Input10_M

Input10_P

Input9_M

Input9_P

Input8_M

Input8_P

Input1_M

Input1_P

Input4_M

Input4_P

Input3_M

Input3_P

Input2_M

Input2_P

Input5_M

Input5_P

Input6_M

Input6_P

Input7_M

Input7_P

Input22_M

Input22_P

Input19_M

Input19_P

Input20_M

Input20_P

Input21_M

Input21_P

Input23_M

Input23_P

Input18_M

Input18_P

Input17_M

Input17_P

Input16_M

Input16_P

Input24_M

Input24_P

Input25_M

Input25_P

Input26_M

Input26_P

Input27_M

Input27_P

Input16_P

Input16_M

Input17_P

Input17_M

Input18_P

Input18_M

Input25_P

Input25_M

Input23_P

Input23_M

Input22_P

Input22_M

Input24_P

Input24_M

Input20_P

Input20_M

Input21_P

Input21_M

Input19_P

Input19_M

Input27_P

Input27_M

Input26_P

Input26_M

U1-2

XC4VLX25-SF363-BGA

U1-2

XC4VLX25-SF363-BGA

IO_L1P_5

B15

IO_L1N_5

A15

IO_L2P_5

A16

IO_L2N_5

B16

IO_L3P_5

C15

IO_L3N_5

C16

IO_L4P_5

B17

IO_L4N_VREF_5

C17

IO_L5P_5

D16

IO_L5N_5

E16

IO_L6P_5

A18

IO_L6N_5

B18

IO_L7P_5

D17

IO_L7N_5

D18

IO_L8P_CC_LC_5

B19

IO_L8N_CC_LC_5

C20

IO_L9P_CC_LC_5

F18

IO_L9N_CC_LC_5

E18

IO_L10P_5

C18

IO_L10N_5

C19

IO_L1

1P_5

F16

IO_L1

1N_5

F17

IO_L12P_5

D19

IO_L12N_VREF_5

E19

IO_L13P_5

G16

IO_L13N_5

G17

IO_L14P_5

E20

IO_L14N_5

F20

IO_L15P_5

H16

IO_L15N_5

H17

IO_L16P_5

F19

IO_L16N_5

G19

IO_L17P_5

J17

IO_L17N_5

J18

IO_L18P_5

H20

IO_L18N_5

G20

IO_L19P_5

J15

IO_L19N_5

J16

IO_L20P_5

H18

IO_L20N_VREF_5

H19

IO_L21P_5

K16

IO_L21N_5

K17

IO_L22P_5

K20

IO_L22N_5

J19

IO_L23P_VRN_5

L16

IO_L23N_VRP_5

L17

IO_L24P_CC_LC_5

K18

IO_L24N_CC_LC_5

K19

IO_L25P_CC_LC_5

M17

IO_L25N_CC_LC_5

M18

IO_L26P_5

M20

IO_L26N_5

L20

IO_L27P_5

M15

IO_L27N_5

M16

IO_L28P_5

M19

IO_L28N_VREF_5

L19

IO_L29P_5

N16

IO_L29N_5

N17

IO_L30P_5

N18

IO_L30N_5

N19

IO_L31P_5

P16

IO_L31N_5

P17

IO_L32P_5

P19

IO_L32N_5

P20

CONN_QSH_30X2-D-A

100

101

102

103

104

105

106

107

108

109

120

Schematics and Bill of Materials

www.ti.com

Figure 16. Schematic Diagram Page 4

TSW1200EVM: High-Speed LVDS Deserializer and Analysis System

SLAU212A – April 2007 – Revised August 2008

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Содержание TSW1200EVM

Страница 1: ...1200 User Interface Installation 13 8 Hardware Device Manager 14 9 Found New Hardware Windows 15 10 User Interface Initial Setup Screen 16 11 User Interface Single FFT format 20 12 User Interface Time...

Страница 2: ...EW is a trademark of National Instruments Corporation MATLAB is a trademark of The MathWorks Inc Xilinx is a trademark of Xilinx Inc TSW1200EVM High Speed LVDS Deserializer and Analysis System 2 SLAU2...

Страница 3: ...DS line one bit at a time at a higher data rate than the sample rate of the ADC The firmware in the FPGA on the TSW1200 is designed to accommodate both parallel DDR formats and serial LVDS formats alt...

Страница 4: ...e ended CMOS output The TSW1200 FPGA has enough FIFO buffer to capture as much as a 65536 sample record length from the continuous sample data stream coming from the LVDS ADC interface The TSW1200 FPG...

Страница 5: ...N TI recommends that the black banana jack J14 be connected to a bench ground even if the 6 V external power brick is connected to J7 Intermittent loss of the USB connection can sometimes be observed...

Страница 6: ...FPGA Bit file CFG1 jumper J10 set to LO and jumper J11 set to HI is defined for use with ADC EVMs that employ a parallel LVDS DDR dual data rate format Bit file CFG2 is defined for use with ADC EVMs t...

Страница 7: ...one JTAG device connected to the TDI of the next JTAG device The normal setting of the JTAG jumpers is to connect the TDI of the JTAG connector to the TDI pin of the FPGA EEPROM through jumper J12 pi...

Страница 8: ...derived from the onboard oscillator LED D2 labeled DCM on the TSW1200 silkscreen which is an abbreviation for the digital clock manager block of logic in the FPGA flashes when an LVDS clock from the...

Страница 9: ...amtec connector Fourteen LVDS data pairs plus two LVDS clock pairs have a defined position in the connector pinout that is common between the TSW1200EVM and many TI ADC EVMs For the parallel LVDS DDR...

Страница 10: ...he operational mode of the ADC under evaluation There SPI signals are by default not connected on the ADC EVM until a 0 resistor is installed on the EVM to enable control of the SPI port from the TSW1...

Страница 11: ...ure depth for an FFT on a million continuous data samples or more For this the output header posts are available so that a logic analyzer can be used to capture ADC data in real time The pinout of the...

Страница 12: ...1200 Installation CD and are installed during the installation process The USB is accessed as a virtual communication port VCP and shows up in the Hardware Device Manager as TSW1200 under COM ports an...

Страница 13: ...200 User Interface Installation If the TSW1200 user interface software is being installed on a machine that has an older version TI recommends that you first remove the old TSW1200 installation using...

Страница 14: ...onnected the TSW1200EVM to the PC the TSW1200 can be located in the Hardware Device Manager as shown in Figure 8 The TSW1200 appears as TSW1200 as a COM port Each time the USB cable is connected it is...

Страница 15: ...iguration for the PC If the Found New Hardware Wizard does appear again when the USB cable is reconnected follow the same responses to the dialog boxes as when the TSW1200 was first installed Figure 9...

Страница 16: ...chosen from the test pulldown menu Figure 10 User Interface Initial Setup Screen The toolbar contains options and settings that are independent of the device selected for test or the test to be perfor...

Страница 17: ...st Later revisions of the TSW1200 software will allow for setting test parameters for a Dual Tone FFT test and the ACPR test For a Single Tone FFT test the RMS line may be enabled or disabled When ena...

Страница 18: ...nce statistics Time Domain displays the raw captured data in the format of a logic analyzer display and output level over time In the Window Display drop down menu the user chooses a windowing functio...

Страница 19: ...marker to any place in the power spectrum such as a noise spur that is not already marked as a harmonic By default this additional marker initially goes to the highest spur that is not identified as...

Страница 20: ...d third fourth and fifth harmonics of the input frequency and the user selectable marker are displayed in either dBFS or dBc Test setup Input parameters relevant to the test are repeated particularly...

Страница 21: ...n results window In the upper half of the window the arithmetic value of the sample is represented on the vertical scale In the lower half of the window the individual bits of the data are displayed a...

Страница 22: ...e can open a com port to the USB channel and can perform the register reads and writes to the TSW1200 hardware One common request for another user interface is MATLAB as the user might then want to us...

Страница 23: ...1 2 C17 1uF C17 1uF 1 2 R109 300 R109 300 C44 01uF C44 01uF 1 2 C43 1uF C43 1uF 1 2 R58 24 3K R58 24 3K C349 10uF 10 16V C349 10uF 10 16V 1 2 C53 10uF 16V 10 LOW ESR C53 10uF 16V 10 LOW ESR C49 1uF C4...

Страница 24: ...SDA 10 GND8 8 P3 3 30 P3 1 31 P3 0 32 GND28 28 X2 26 RI CP 16 DCD 15 VCC25 25 U1 4 XC4VLX25 SF363 BGA U1 4 XC4VLX25 SF363 BGA IO_L20P_7 R19 IO_L20N_VREF_7 R20 IO_L21P_7 R15 IO_L21N_7 R16 IO_L23P_VRN_7...

Страница 25: ...F C79 10uF J10 HEADER 3 J10 HEADER 3 1 2 3 J2 J2 2 4 6 8 10 12 14 1 3 5 7 9 11 13 C86 1uF C86 1uF 1 2 R3 0 ohm R3 0 ohm C83 3 3uF C83 3 3uF R52 4 7K R52 4 7K R2 0 ohm R2 0 ohm R33 1K R33 1K Q3 DTC114E...

Страница 26: ...6 IO_L4P_5 B17 IO_L4N_VREF_5 C17 IO_L5P_5 D16 IO_L5N_5 E16 IO_L6P_5 A18 IO_L6N_5 B18 IO_L7P_5 D17 IO_L7N_5 D18 IO_L8P_CC_LC_5 B19 IO_L8N_CC_LC_5 C20 IO_L9P_CC_LC_5 F18 IO_L9N_CC_LC_5 E18 IO_L10P_5 C18...

Страница 27: ...10 8 9 J18 HDR 16X2 MALE 100CTR TI_SILKTEXT J18 HDR 16X2 MALE 100CTR TI_SILKTEXT 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 J6 HEADER MALE 20x2 POS 100 VERT...

Страница 28: ...onic 10 10V 2 C77 C78 22 pF 603 GRM1885C2A220JA01D Murata 5 100V 2 C81 C85 0 1 F 603 ECJ 1VB1H104K Panasonic 10 50V 2 C82 C84 2 2 F 603 ECJ 1VB1A225K Panasonic 10 10V 1 C83 3 3 F TANT_B TAJB335K016R A...

Страница 29: ...o 1 1 10W 8 R27 R30 22 603 RC0603FR 0722RL Yageo 1 1 10W R60 R63 6 R33 R34 R37 R 1K 603 ERJ 3EKF1001V Panasonic 1 1 10W 38 R46 R47 2 R35 R36 100 603 ERJ 3EKF1000V Panasonic 1 1 10W 1 R45 100K 603 ERJ...

Страница 30: ...I Provide pad 1 U14 PTH03000W SMD_PWRMOD_EUT5 PTH03000WAS TI TI Provide 1 U15 TPS73225 SOT23 DBV5 TPS73225DBVT TI TI Provide 1 Y1 12MHz w 18pF smd_xtal_AMB3B ABM3B 12 000MHZ 10 1 Abracon U T 4 Screw 4...

Страница 31: ...m Circuit Board Layout and Layer Stackup Figure 19 TSW1200C Layout Layer Two SLAU212A April 2007 Revised August 2008 TSW1200EVM High Speed LVDS Deserializer and Analysis System 31 Submit Documentation...

Страница 32: ...ard Layout and Layer Stackup www ti com Figure 20 TSW1200C Layout Power Plane 32 TSW1200EVM High Speed LVDS Deserializer and Analysis System SLAU212A April 2007 Revised August 2008 Submit Documentatio...

Страница 33: ...Circuit Board Layout and Layer Stackup Figure 21 TSW1200C Layout Ground Plane SLAU212A April 2007 Revised August 2008 TSW1200EVM High Speed LVDS Deserializer and Analysis System 33 Submit Documentatio...

Страница 34: ...Board Layout and Layer Stackup www ti com Figure 22 TSW1200C Layout Layer 5 34 TSW1200EVM High Speed LVDS Deserializer and Analysis System SLAU212A April 2007 Revised August 2008 Submit Documentation...

Страница 35: ...i com Circuit Board Layout and Layer Stackup Figure 23 TSW1200C Layer 6 SLAU212A April 2007 Revised August 2008 TSW1200EVM High Speed LVDS Deserializer and Analysis System 35 Submit Documentation Feed...

Страница 36: ...Board Layout and Layer Stackup www ti com Figure 24 TSW1200C Bottom Layer 36 TSW1200EVM High Speed LVDS Deserializer and Analysis System SLAU212A April 2007 Revised August 2008 Submit Documentation F...

Страница 37: ...com Circuit Board Layout and Layer Stackup Figure 25 Circuit Board Stackup SLAU212A April 2007 Revised August 2008 TSW1200EVM High Speed LVDS Deserializer and Analysis System 37 Submit Documentation F...

Страница 38: ...uct This notice contains important safety information about temperatures and voltages For additional information on TI s environmental and or safety programs please contact the TI application engineer...

Страница 39: ...siness practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product wo...

Страница 40: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments TSW1200EVM...

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