Functionality
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The FPGA firmware for the TSW1200 generally consists of two major functions: the LVDS ADC interface
and the FIFO capture. The LVDS ADC interface supports either the various parallel DDR interfaces or the
various serial interfaces as previously described. The LVDS ADC interface code in the FPGA reformats
the data into a standard single-ended parallel data word with sample clock. This parallel sample word plus
clock is output continuously to header posts on the TSW1200 for capture by a logic analyzer. The parallel
data word with sample clock also is presented to the FIFO capture logic. Note that for parallel DDR data
formats, the header output posts are not enabled by default, as the data rate (up to a 500-MHz sample
rate) is often too fast to be feasible for a single-ended CMOS output.
The TSW1200 FPGA has enough FIFO buffer to capture as much as a 65536-sample record length from
the continuous sample data stream coming from the LVDS ADC interface. The TSW1200 FPGA design
includes a UART function that can transfer data to and from a USB interface device on the TSW1200
board. The USB interface device on the TSW1200EVM connects to a personal computer (PC) running
Windows™ over a standard USB cable. The operation of the FIFO capture logic is controlled by writes
from the PC USB port to a register map defined within the FPGA. The user interface software on the PC
selects by register operations such things as record length of data to capture, which channel of an ADC to
capture from, and then the user interface software downloads the captured data from the TSW1200 for
processing in the form of an FFT or time-domain display.
TSW1200EVM: High-Speed LVDS Deserializer and Analysis System
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SLAU212A – April 2007 – Revised August 2008
