2.7
Received-Message-Pending Register (CANRMP)
Received-Message-Pending Register (CANRMP)
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If mailbox
n
contains a received message, the bit RMP[
n
] of this register is set. These bits can be reset
only by the CPU and set by the internal logic. A new incoming message overwrites the stored one if the
OPC[
n
](OPC.31-0) bit is cleared, otherwise the next mailboxes are checked for a matching ID. If a mailbox
is overwritten, the corresponding status bit RML[
n
] is set. The bits in the CANRMP and the CANRML
registers are cleared by a write to register CANRMP, with a 1 at the corresponding bit location. If the CPU
tries to reset a bit and the CAN tries to set the bit at the same time, the bit is set.
The bits in the CANRMP register can set GMIF0/GMIF1 (GIF0.15/GIF1.15) if the corresponding interrupt
mask bit in the CANMIM register is set. The GMIF0/GMIF1 bit initiates an interrupt.
Figure 2-7. Received-Message-Pending Register (CANRMP)
31
0
RMP[31:0]
RC-0
LEGEND: RC = Read/Clear; -
n
= value after reset
Table 2-7. Received-Message-Pending Register (CANRMP) Field Descriptions
Bit
Field
Value
Description
31:0
RMP[31:0]
Received-message-pending bits
1
If mailbox
n
contains a received message, bit RMP[
n
] of this register is set.
0
The mailbox does not contain a message.
eCAN Registers
32
SPRU074F – May 2002 – Revised January 2009