3.5
CAN Power-Down Mode
3.5.1 Entering and Exiting Local Power-Down Mode
3.5.2 Precautions for Entering and Exiting Device Low-Power Modes (LPM)
CAN Power-Down Mode
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2. The PIEACK bit corresponding corresponding to the CAN module must be written with a 1, which can
be accomplished with the following C language statement:
PieCtrlRegs.PIEACK.bit.ACK9 = 1; // Enables PIE to drive a pulse into the CPU
3. The interrupt line into the CPU corresponding to the CAN module must be enabled, which can be
accomplished with the following C language statement:
IER |= 0x0100; // Enable INT9
4. The CPU interrupts must be enabled globally by clearing the INTM bit.
A local power-down mode has been implemented where the CAN module internal clock is de-activated by
the CAN module itself.
During local power-down mode, the clock of the CAN module is turned off (by the CAN module itself) and
only the wake-up logic is still active. The other peripherals continue to operate normally.
The local power-down mode is requested by writing a 1 to the PDR (CANMC.11) bit, allowing transmission
of any packet in progress to complete. After the transmission is completed, the status bit PDA (CANES.3)
is set. This confirms that the CAN module has entered the power-down mode.
The value read on the CANES register is 0x08 (PDA bit is set). All other register read accesses deliver the
value 0x00.
The module leaves the local power-down mode when the PDR bit is cleared or if any bus activity is
detected on the CAN bus line (if the wake-up-on bus activity is enabled).
The automatic wake-up-on bus activity can be enabled or disabled with the configuration bit WUBA of
CANMC register. If there is any activity on the CAN bus line, the module begins its power-up sequence.
The module waits until it detects 11 consecutive recessive bits on the CANRX pin and then it goes
bus-active.
Note:
The first CAN message, which initiates the bus activity, cannot be received. This means that
the first message received in power-down and automatic wake-up mode is lost.
After leaving the sleep mode, the PDR and PDA bits are cleared. The CAN error counters remain
unchanged.
If the module is transmitting a message when the PDR bit is set, the transmission is continued until a
successful transmission, a lost arbitration, or an error condition on the CAN bus line occurs. Then, the
PDA bit is activated so the module causes no error condition on the CAN bus line.
To implement the local power-down mode, two separate clocks are used within the CAN module. One
clock stays active all the time to ensure power-down operation (i.e., the wake-up logic and the write and
read access to the PDA (CANES.3) bit). The other clock is enabled depending on the setting of the PDR
bit.
The 28x DSP features two low-power modes, STANDBY and HALT, in which the peripheral clocks are
turned off. Since the CAN module is connected to multiple nodes across a network, you must take care
before entering and exiting device low-power modes such as STANDBY and HALT. A CAN packet must
be received in full by all the nodes; therefore, if transmission is aborted half-way through the process, the
aborted packet would violate the CAN protocol resulting in all the nodes generating error frames. The
node exiting LPM should do so unobtrusively. For example, if a node exits LPM when there is traffic on
the CAN bus it could “see” a truncated packet and disturb the bus with error frames.
The following points must be considered before entering a device low-power mode:
1. The CAN module has completed the transmission of the last packet requested.
80
eCAN Configuration
SPRU074F – May 2002 – Revised January 2009
