Texas Instruments Sitara AM1335 Series, Руководство пользователя

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All Errata Listed With Silicon Revision Number
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2 All Errata Listed With Silicon Revision Number
Advisories are numbered in the order in which they were added to this document. Some advisory numbers
may be moved to the next revision and others may have been removed because the design exception
was fixed or documented in the device-specific data manual or peripheral user's guide. When items are
moved or deleted, the remaining numbers remain the same and are not re-sequenced.
Table 3. All Usage Notes
SILICON REVISION AFFECTED
NUMBER TITLE
1.0 2.0 2.1
Section 3.1.1 LCD: Color Assignments of LCD_DATA Terminals X X X
DDR3: JEDEC Compliance for Maximum Self-Refresh
Section 3.1.2 X X X
Command Limit
Section 3.1.3 Boot: USB Boot ROM Code Uses Default DATAPOLARITY X X X
Boot: Multiplexed Signals GPMC_WAIT0, GMII2_CRS, and
Section 3.1.4 X
RMII2_CRS_DV Cause NAND Boot Issue
Section 3.1.5 Pin Multiplexing: Valid IO Sets and Restrictions X X X
Boot: Multiplexed Signals GPMC_WAIT0 and GMII2_CRS
Section 3.1.6 X X
Cause NAND Boot Issue
OSC1: RTC_XTALIN Terminal Has an Internal Pull-up
Section 3.1.7 X X X
Resistor When OSC1 is Disabled
Table 4. All Design Exceptions to Functional Specifications
SILICON REVISION AFFECTED
NUMBER TITLE
1.0 2.0 2.1
DDR2, DDR3, mDDR PHY: Control and Status Registers
Advisory 1.0.1 X X X
Configured for Write Only
Debug Subsystem: EMU[4:2] Signals Are Not Available by
Advisory 1.0.2 X X X
Default After Reset
Debug Subsystem: Internal Inputs Tied-off to the Wrong
Advisory 1.0.3 X X X
Value
Advisory 1.0.4 PRU-ICSS: Clock Domain Crossing (CDC) Issue X
Advisory 1.0.5 RTC: 32.768-kHZ Clock is Gating Off X
EXTINTn: Input Function of the EXTINTn Terminal is
Advisory 1.0.6 X
Inverted
Advisory 1.0.7 Boot: Ethernet Boot ROM Code PHY Link Speed Detection X
Boot: Ethernet Boot ROM Code Sends an Incorrect Vendor
Advisory 1.0.8 X
Class Identifier in BOOTP Packet
Ethernet Media Access Controller and Switch Subsystem:
Advisory 1.0.9 C0_TX_PEND and C0_RX_PEND Interrupts Not Connected X
to ARM Cortex-A8
GMII_SEL Register: RGMII1_IDMODE and
Advisory 1.0.10 RGMII2_IDMODE Bits Reset to Non-supported Mode of X
Operation
USB: Attached Non-compliant USB Device that Responds
Advisory 1.0.11 X
to Spurious Invalid Short Packet May Lock Up Bus
UART: Extra Assertion of FIFO Transmit DMA Request,
Advisory 1.0.12 X X X
UARTi_DMA_TX
USB: Data May be Lost When USB Subsystem is Operating
Advisory 1.0.13 in DMA Mode and More Than One Endpoint is Transferring X
Data
GMII_SEL and CPSW Related Pad Control Registers:
Advisory 1.0.14 Context of These Registers is Lost During Transitions of X
PD_PER
ARM Cortex-A8: OPP50 Operation on MPU Domain Not
Advisory 1.0.15 X
Supported
6 SPRZ360F – October 2011 – Revised November 2013
Sitara™ AM335x ARM
®
Cortex™-A8 Microprocessors (MPUs) (Silicon Revision
2.1, 2.0, 1.0) Submit Documentation Feedback
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