Usage Notes and Known Design Exceptions to Functional Specifications
3.1.5
Pin Multiplexing: Valid IO Sets and Restrictions
The AM335x device contains many peripheral interfaces. In order to reduce package size and lower
overall system cost while maintaining maximum functionality, many of the AM335x terminals can multiplex
up to eight signal functions. Although there are many combinations of pin multiplexing that are possible,
only a certain number of sets, called IO Sets, are valid due to timing limitations. These valid IO Sets were
carefully chosen to provide many possible application scenarios for the user.
Texas Instruments has developed a Windows
®
-based application called Pin Mux Utility that helps a
system designer select the appropriate pin-multiplexing configuration for their AM335x-based product
design. The Pin Mux Utility provides a way to select valid IO Sets of specific peripheral interfaces to
ensure the pin multiplexing configuration selected for a design only uses valid IO Sets supported by the
AM335x device.
A few IO Sets have additional restrictions not defined in the Pin Mux Utility. These additional restrictions
are described below:
•
MMC0, MMC1, MMC2 Interfaces
–
Only Standard (STD) and High Speed (HS) modes are supported. SDR12, SDR25, SDR50 modes
as defined in SD3.0 specification are not supported.
•
GEMAC_CPSW Interface
–
Operation of GEMAC_CPSW is not supported for OPP50.
3.1.6
Boot: Multiplexed Signals GPMC_WAIT0 and GMII2_CRS Cause NAND Boot Issue
The AM335x device multiplexes the GPMC_WAIT0 and GMII2_CRS signals on the same terminal. This
causes a problem when the system must support NAND boot while an MII Ethernet PHY is connected to
port 2 of the Ethernet media access controller and switch (CPSW). The GPMC_WAIT0 signal is required
for NAND boot. The GMII2_CRS signal is required by the MII Ethernet PHY and the only pin multiplexing
option for these signals is GPMC_WAIT0.
In this case, there are two sources that need to be connected to the GPMC_WAIT0 terminal. The NAND
READY or BUSY output must source the GPMC_WAIT0 terminal during NAND boot and the MII CRS
output must source the GPMC_WAIT0 terminal when the application software is using port 2 of the
CPSW. Therefore, a GPIO-controlled external 2-to-1 multiplexer must be implemented in the system to
select between the two sources. The GPIO selected to control the 2-to-1 multiplexer needs to have an
internal or external resistor that selects the NAND READY or BUSY output as soon as power is applied
and remains in that state until the application software initializes the CPSW.
The TI TS5A3157 SPDT analog switch is an example device that can be used as a 2-to-1 multiplexer.
This device inserts minimum propagation delay to the signal path since it is an analog switch. The
propagation delay inserted by the 2-to-1 multiplexer must be analyzed to confirm it does not cause timing
violations for the respective interface.
The NAND, Ethernet PHY, AM335x VDDSHV1, AM335x VDDSHV3 (when using the ZCZ package), and
2-to-1 multiplexer IO power supply domains may need to operate at the same voltage since they share
common signals.
10
SPRZ360F – October 2011 – Revised November 2013
Sitara™ AM335x ARM
®
Cortex™-A8 Microprocessors (MPUs) (Silicon
Revision 2.1, 2.0, 1.0)
Copyright © 2011–2013, Texas Instruments Incorporated
