Usage Notes and Known Design Exceptions to Functional Specifications
Advisory 1.0.10
GMII_SEL Register: RGMII1_IDMODE and RGMII2_IDMODE Bits Reset to Non-
supported Mode of Operation
Revisions Affected
1.0
Details
The reset state of RGMII1_IDMODE (bit 4) and RGMII2_IDMODE (bit 5) in the
GMII_SEL register enables internal delay mode on the transmit clock of the respective
RGMII port. The AM335x device does not support internal delay mode, so
RGMII1_IDMODE and RGMII2_IDMODE must be set to 1b.
Workarounds
Many RGMII Ethernet PHYs provide an internal delay mode that may be enabled to
insert delays required to meet the setup and hold timing requirements of the AM335x
device and attached RGMII PHY. A timing analysis is recommended before the printed
circuit board (PCB) design has been completed, in case it is necessary to insert
additional delays on the RGMII signals connecting the AM335x device and attached
RGMII PHY.
It is necessary to insert PCB delays if the RGMII PHY being connected to the AM335x
device does not support internal delay mode. A complete timing analysis is required to
determine the optimum delay of each PCB signal trace.
17
SPRZ360F – October 2011 – Revised November 2013
Sitara™ AM335x ARM
®
Cortex™-A8 Microprocessors (MPUs) (Silicon
Revision 2.1, 2.0, 1.0)
Copyright © 2011–2013, Texas Instruments Incorporated
